Efficient power darlington device configuration

Claim 2

A power transistor comprising: a first region of a first conductivity type having a first surface, said first region including a collector region; a base region of a second conductivity type in said first region at said first surface, said base region including first and second base subregions at said first surface; a first inner subregion of said first region at said first surface, said first inner subregion being substantially surrounded by said first and second subregions; an emitter region of said first conductivity type in said base region at said first surface, said emitter region being heavily doped and including first and second emitter subregions in said first base subregion and third and fourth emitter subregions in said second base subregion, said first, second, third and fourth emitter subregions being essentially elongated, said first and second emitter subregions lying essentially in line, said first and third emitter subregions being essentially parallel to said second and fourth emitter subregions; second and third regions of said first conductivity type in said first region at said first surface, said second and third regions being relatively heavily doped, said third region being within said first inner subregion of said first region, and said second region being outside of said first inner subregion, said second region including first and second ballast resistors, and said third region including a third ballast resistor; a first passivation layer on said first surface, said first passivation layer having therein a base preohmic opening on said first and second base subregions, and at least first, second, third and fourth emitter preohmic openings over, respectively, said first, second, third and fourth emitter subregions, said base preohmic opening substantially surrounding said first, second, third and fourth emitter subregions; base metallization means contacting said base region through said base preohmic opening; and emitter metallization means contacting said first, second, third and fourth emitter subregions, respectively, through said first, second, third and fourth emitter preohmic openings, said emitter metallization means connecting said first and second ballast resistors in series, respectively, with said first and third emitter subregions, and also connecting said third ballast resistor in series with both said second and fourth emitter subregions, said emitter metallization means including an emitter terminal, said first, second and third ballast resistors being connected to said emitter terminal.

Claim 3

The power transistor as recited in claim 1 further comprising: a buried layer of said first conductivity type, said buried layer being relatively heavily doped, and having an extending portion extending into said first region, said buried layer also extending laterally beyond said base region at one side thereof; a relatively heavily doped, elongated collector contact region of said first conductivity type extending through said first region to said extending portion of said buried layer; a substrate of said second conductivity type, said first region being on said substrate, and said buried layer extending into said substrate; and, an isolation region of said second conductivity type extending through said first region to said substrate, said isolation region being relatively heavily doped, said isolation region also being closed, and acting to isolate said collector region.

Claim 4

The power transistor as recited in claim 1 wherein said first conductivity type is N type and said Second conductivity type is P type.

Claim 5

The power transistor as recited in claim 1 further including: at least an additional first base subregion and an additional second base subregion in said base region, each said additional first base subregion and each said additional second base subregion, respectively, together substantially surrounding, respectively, an additional subregion; an additional first emitter subregion and an additional second emitter subregion in each said additional first base subregion, and an additional third emitter subregion and an additional fourth emitter subregion in each said second base subregion, each said additional first and third emitter subregion being substantially in line with said first and third emitter subregions, and each said additional second and fourth emitter subregions being substantially in line with said second and fourth emitter subregions.

Claim 6

An integrated circuit power Darlington transistor device comprising: a P type substrate; a first N type region on said P type substrate, said first N type region including therein an N type collector region, said first N type region having a first surface thereof; an N type buried layer between said P type substrate and said first N type region extending into said P type substrate and into said first N type region, said N type buried layer being relatively heavily doped, said buried layer also being elongated; a closed, P type isolation region extending through said first N type region around said N type buried layer to said P type substrate, acting to isolate said N type collector region; a P type first base region in said N type collector region over said N type buried layer region, an elongated, extending portion of said N type buried layer extending laterally beyond said P type base region, said P type base region including first, second, third, fourth, fifth and sixth base subregions; first, second and third inner subregions of said N type collector region at said first surface, said first inner subregion being substantially surrounded at said first surface by said first and second base subregions, said second inner subregion being substantially surrounded at said first surface by said third and fourth base subregions, said third inner subregion being substantially surrounded at said first surface by said fifth and sixth base subregions; a heavily doped N type first emitter region in said P type base region at said first surface, said first N type emitter region including first and second emitter subregions in said first base subregion, third and fourth emitter subregions in said second base subregion, fifth and sixth emitter subregions in said third base subregion, seventh and eighth emitter subregions in said fourth base subregion, ninth and tenth emitter subregions in said fifth base subregion, and eleventh and twelfth emitter subregions in said sixth base subregion, said first, third, fifth, seventh, ninth, and eleventh emitter subregions being elongated and substantially in line, and said second, fourth, sixth, eighth, tenth, and twelfth emitter subregions being elongated and substantially in line; first, second and third N type ballast resistors in said first, second and third inner subregions, respectively, said first, second and third ballast resistors each having, respectively, first and second ends thereof; fourth and fifth N type ballast resistors adjacent said first and second emitter subregions, respectively, sixth and seventh N type ballast resistors adjacent said fifth and seventh emitter subregions, respectively, and ninth and eleventh N type ballast resistors adjacent said ninth and eleventh emitter subregions, respectively, said fourth, fifth, sixth, seventh, eighth, and ninth N type ballast resistors each having, respectively, first and second ends thereof; a passivation layer on said first surface, said passivation layer having thereIn a separate emitter preohmic opening, respectively, over each of said emitter subregions, a separate ballast resistor preohmic opening over each end of each of said ballast resistors, and a base preohmic opening, said base preohmic opening substantially surrounding each of said emitter subregions at said surface; a driver transistor in said first N type region, within said closed P type isolation region, including a second base region and a second emitter region therein; base metallization means on said passivation layer contacting said P type base region through said base preohmic opening and also contacting said second emitter; and emitter metallization means on said passivation layer contacting said emitter subregions through said emitter preohmic openings and contacting said ballast resistors through said ballast resistor preohmic openings, said emitter metallization including an emitter terminal, said emitter terminal contacting said first end of each of said N type ballast resistors, said emitter metallization also connecting said second and fourth emitter subregions to said second end of said first ballast resistor, and connecting said sixth and eighth emitter subregions to said second end of said second ballast resistor, and connecting said tenth and twelfth emitter subregions to said second end of said third ballast resistor, and connecting said first, third, fifth, seventh, ninth and eleventh emitter subregions to said second ends of said fourth, fifth, sixth, seventh, eighth and ninth ballast resistors, respectively.

Claim 7

An integrated circuit power Darlington transistor device comprising: a P type substrate; a first N type region on said P type substrate, said first N type region including therein an N type collector region, said first N type region having a first surface thereof; an N type buried layer between said P type substrate and said first N type region extending into said P type substrate and into said first N type region, said N type buried layer being relatively heavily doped, said buried layer also being elongated; a closed, P type isolation region extending through said first N type region around said N type buried layer to said P type substrate, acting to isolate said N type collector region; a P type first base region in said N type collector region over said N type buried layer region, an elongated, extending portion of said N type buried layer extending laterally beyond said P type base region, said P type base region including first, second, third, fourth, fifth and sixth base subregions; first, second and third inner subregions of said N type collector region at said first surface, said first inner subregion being substantially surrounded at said first surface by said first and second base subregions, said second inner subregion being substantially surrounded at said first surface by said third and fourth base subregions, said third inner subregion being substantially surrounded at said first surface by said fifth and sixth base subregions; a heavily doped N type first emitter region in said P type base region at said first surface, said first N type emitter region including first and second emitter subregions in said first base subregion, third and fourth emitter subregions in said second base subregion, fifth and sixth emitter subregions in said third base subregion, seventh and eighth emitter subregions in said fourth base subregion, ninth and tenth emitter subregions in said fifth base subregion, and eleventh and twelfth emitter subregions in said sixth base subregion, said first, third, fifth, seventh, ninth, and eleventh emitter subregions being elongated and substantially in line, and said second, fourth, sixth, eighth, tenth, and twelfth emitter subregions being elongated and substantially in line; first, second and third N type ballast resistors in said first, second and third inner subregions, respectively, said first, second and third ballast resistors each having, respectively, first and second ends thereof; fourth and fifth N type ballast resistors adjacent said first and second emitter subregions, respectively, sixth and seventh N type ballast resistors adjacent said fifth and seventh emitter subregions, respectively, and ninth and eleventh N type ballast resistors adjacent said ninth and eleventh emitter subregions, respectively, said fourth, fifth, sixth, seventh, eighth, and ninth N type ballast resistors each having, respectively, first and second ends thereof; a passivation layer on said first surface, said passivation layer having thereIn a separate emitter preohmic opening, respectively, over each of said emitter subregions, a separate ballast resistor preohmic opening over each end of each of said ballast resistors, and a base preohmic opening, said base preohmic opening substantially surrounding each of said emitter subregions at said surface; a driver transistor in said first N type region, within said closed P type isolation region, including a second base region and a second emitter region therein; base metallization means on said passivation layer contacting said P type base region through said base preohmic opening and also contacting said second emitter; and emitter metallization means on said passivation layer contacting said emitter subregions through said emitter preohmic openings and contacting said ballast resistors through said ballast resistor preohmic openings, said emitter metallization including an emitter terminal, said emitter terminal contacting said first end of each of said N type ballast resistors, said emitter metallization also connecting said second and fourth emitter subregions to said second end of said first ballast resistor, and connecting said sixth and eighth emitter subregions to said second end of said second ballast resistor, and connecting said tenth and twelfth emitter subregions to said second end of said third ballast resistor, and connecting said first, third, fifth, seventh, ninth and eleventh emitter subregions to said second ends of said fourth, fifth, sixth, seventh, eighth and ninth ballast resistors, respectively.