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US3810301A
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Method for making an integrated circuit apparatus
Assignee: Centre de Recherche Industrielle du Quebec CRIQ
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Filing: 1972-08-31
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Granted: 1974-05-14
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Expires: 1992-08-31
Abstract
Abstract The method consists in subdividing an entire substrate into many independent and identical circuit arrays with each array containing an identical programmable section, in programming the first array to respond to a certain set of electrical impulses, in testing the array for electrical function: if the array is good, proceeding with the programming and testing of the programmable section of the second array using another set of electrical impulses; if the array is faulty, proceeding with the programming and testing of the programmable section of the second array with the same set of electrical impulses used for the previous faulty array; then, repeating the above programming and testing steps for the remaining circuit arrays of the substrate using different sets of electrical impulses; and then establishing connection between the system connect lines of each array.
Inventors
- 👤 R Cook
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:29
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; G; G11; G11C; G11C29/00; G11C29/006; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26; G11C29/28; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49004
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
223 words
A method for making integrated circuits apparatus comprising the steps of a. providing a plurality of identical and independent circuit arrays formed on a substrate, each said array containing a programmable section having conductive paths that can be selectively opened for establishing a unique array identity and system connect lines; b. programming the programmable section by selectively opening said conductive paths of a first circuit array to respond to a predetermined set of electrical impulses and so establish a unique array identity; c. testing said first array to thereafter i. proceed with the programming of the programmable section of a second circuit array and testing said second circuit array, if said first array is good, using a second predetermined set of electrical impulses to establish a unique array identity; or ii. proceed with the programming of the programmable section of a second circuit array and testing said second circuit array, if said first array is faulty, using said first predetermined set of electrical impulses to establish an array identity identical with said unique array identity of said faulty first array; d. repeating the above programming and testing steps for the remaining circuit arrays using different sets of electrical impulses; e. establishing connection of the system connect lines of the circuit arrays, and f. opening the connection between faulty arrays and system connect lines.
Claim 2
Independent Claim
223 words
A method for making integrated circuits apparatus comprising the steps of a. providing a plurality of identical and independent circuit arrays formed on a substrate, each said array containing a programmable section having conductive paths that can be selectively opened for establishing a unique array identity and system connect lines; b. programming the programmable section by selectively opening said conductive paths of a first circuit array to respond to a predetermined set of electrical impulses and so establish a unique array identity; c. testing said first array to thereafter i. proceed with the programming of the programmable section of a second circuit array and testing said second circuit array, if said first array is good, using a second predetermined set of electrical impulses to establish a unique array identity; or ii. proceed with the programming of the programmable section of a second circuit array and testing said second circuit array, if said first array is faulty, using said first predetermined set of electrical impulses to establish an array identity identical with said unique array identity of said faulty first array; d. repeating the above programming and testing steps for the remaining circuit arrays using different sets of electrical impulses; e. establishing connection of the system connect lines of the circuit arrays, and f. opening the connection between faulty arrays and system connect lines.
Claim 3
Dependent Claim
45 words
A method as defined in claim 1 wherein said step of opening the connection between faulty arrays and system connect lines includes opening the connection between a faulty array and its system connect lines before proceeding with the programming and testing of a next array.
Claim 4
Dependent Claim
43 words
A method as defined in claim 1 wherein said step of opening the connection between faulty arrays and system connect lines includes opening the connection between faulty arrays and their associated system connect lines after all the chips have been programmed and tested.
Claim 5
Dependent Claim
16 words
A method as defined in claim 3 wherein the location of a faulty array is memorized.
Claim 6
Dependent Claim
26 words
A method as defined in claim 1 further comprising the step of a first metallization for connecting all the associated system connect lines of each array.
Claim 7
Dependent Claim
17 words
A method as defined in claim 5 further comprising a second metallization to thereby increase yield percentage.
Claim 8
Independent Claim
251 words
A method for making integrated circuits apparatus comprising the steps of a. providing a plurality of identical and independent circuit arrays formed on a substrate, each said array containing a programmable section comprising a plurality of fusible links and a logic comparator for establishing a unique array identity to an otherwise identical array and system connect lines; b. programming the programmable section of a first circuit array to respond to a predetermined set of electrical impulses by opening selectable fusible links to give said first array a unique identity; c. testing said first array to thereafter i. proceed with the programming of the programmable section of a second circuit array and testing said second circuit array, if said first array is good, using a second predetermined set of electrical impulses by opening selectable fusible links to give said second array a unique identity; or ii. proceed with the programming of the programmable section of a second circuit array and testing said second circuit array, if said first array is faulty, using said first predetermined set of electrical impulses by opening fusible links corresponding to those opened for said first array to give said second array an identity identical to said first faulty array; d. repeating the above programming and testing steps for the remaining circuit arrays using different sets of electrical impulses and opening selectable fusible links; e. establishing connection of the system connect lines of the circuit arrays, and f. opening the connection between faulty arrays and system connect lines.
Claim 9
Independent Claim
251 words
A method for making integrated circuits apparatus comprising the steps of a. providing a plurality of identical and independent circuit arrays formed on a substrate, each said array containing a programmable section comprising a plurality of fusible links and a logic comparator for establishing a unique array identity to an otherwise identical array and system connect lines; b. programming the programmable section of a first circuit array to respond to a predetermined set of electrical impulses by opening selectable fusible links to give said first array a unique identity; c. testing said first array to thereafter i. proceed with the programming of the programmable section of a second circuit array and testing said second circuit array, if said first array is good, using a second predetermined set of electrical impulses by opening selectable fusible links to give said second array a unique identity; or ii. proceed with the programming of the programmable section of a second circuit array and testing said second circuit array, if said first array is faulty, using said first predetermined set of electrical impulses by opening fusible links corresponding to those opened for said first array to give said second array an identity identical to said first faulty array; d. repeating the above programming and testing steps for the remaining circuit arrays using different sets of electrical impulses and opening selectable fusible links; e. establishing connection of the system connect lines of the circuit arrays, and f. opening the connection between faulty arrays and system connect lines.
References Cited (Backward Citations)
US3423822A
Cited
US3715735A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-05-13 | 1977-11-12 | 1978-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-05-13 | 1981-11-12 | 1982-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-05-13 | 1985-11-12 | 1986-05-14 | $7700.00 | Window Closed / Lapsed |