US3806918A
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Digital phase lock loop
Assignee: Recognition Equipment Inc
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Filing: 1973-03-26
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Granted: 1974-04-23
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Expires: 1993-03-26
Abstract
Abstract A digital loop tracks the frequency and phase of an incoming signal, such as, but limited to an incoming phase encoded signal, to generate a tracking frequency signal. Zero crossings of the incoming signal are converted into trigger pulses for activating and terminating an up/down counter. The counter advances up from a reference level to a count stored in an average count storage register and then reverses direction and counts down to the initial reference. The counter cycle continues until a zero crossing pulse terminates the operation which may be any place along the count cycle of the up/down counter but preferably when the counter counts down to the reference level. A difference between the count in the up/down counter and the initial reference level is stored in an error counter register and this value is added to an accumulated error code stored in an accumulator register. When the accumulated error exceeds a predetermined limit, the count stored in the average count storage register is incremented by an amount and in a direction such that the up/down counter counts down to the reference level at the next zero crossing pulse. When this condition exists the phase lock loop is locked onto the frequency of the incoming signal and varies therewith.
Inventors
- 👤 D Cauthron
- 👤 J Clayton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:57
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
134 words
A digital phase lock system responsive to an input wave, comprising in combination: first means for generating a crossing pulse signal at each occurrence of a predetermined value of the input wave, second means for cyclically counting from a reference level generated clock pulses in response to a first crossing pulse and terminated by a subsequent crossing pulse, count storage means for maintaining an average count of the number of clock pulses generated between subsequent pairs of crossing pulses, means for changing the average count in said storage means in accordance with the average deviation of the counted clock pulses from the reference level for subsequent periods between crossing pulses, and means for varying the counting characteristics of said second means in accordance with the change in the average count in said storage means.
Claim 2
Dependent Claim
134 words
A digital phase lock system responsive to an input wave, comprising in combination: first means for generating a crossing pulse signal at each occurrence of a predetermined value of the input wave, second means for cyclically counting from a reference level generated clock pulses in response to a first crossing pulse and terminated by a subsequent crossing pulse, count storage means for maintaining an average count of the number of clock pulses generated between subsequent pairs of crossing pulses, means for changing the average count in said storage means in accordance with the average deviation of the counted clock pulses from the reference level for subsequent periods between crossing pulses, and means for varying the counting characteristics of said second means in accordance with the change in the average count in said storage means.
Claim 3
Dependent Claim
27 words
A digital phase lock system as set forth in claim 1 including means for resetting said second means to the reference level count between subsequent clock pulses.
Claim 4
Dependent Claim
43 words
A digital phase lock system as set forth in claim 1 wherein said means for changing the average count includes means for storing the deviation of the clock pulses counted by said second means from the reference level at the subsequent crossing pulse.
Claim 5
Dependent Claim
39 words
A digital phase lock system as set forth in claim 3 wherein said means for changing the average count includes means for averaging the deviation of the clock pulses from the reference level for subsequent periods between crossing pulses.
Claim 6
Dependent Claim
38 words
A digital phase lock system as set forth in claim 4 including means responsive to the average deviation of clock pulses from the reference level to vary the count characteristics when said average deviation exceeds a predetermined limit.
Claim 7
Dependent Claim
36 words
A digital phase lock system as set forth in claim 1 including means responsive to the count characteristics of said second means for generating a phase signal having a frequency and phase tracking the input wave.
Claim 8
Dependent Claim
156 words
A digital phase lock system responsive to a phase encoded input wave, comprising in combination: first means for generating a square wave signal related to the phase encoded input data, second means for generating a crossing pulse signal at a predetermined value of the phase encoded input wave, third means for cyclically counting in a positive and negative sense from a reference level generated clock pulses in response to a first crossing pulse and terminated by a subsequent crossing pulse, count storage means for maintaining an average count of the number of counted clock pulses generated between subsequent pairs of crossing pulses, means for changing the average count in said storage means in accordance with average deviation of the counted clock pulses from the reference level for subsequent periods between crossing pulses, and means for varying the counting characteristics of said third means in accordance with the change in the average count in said storage means.
Claim 9
Dependent Claim
156 words
A digital phase lock system responsive to a phase encoded input wave, comprising in combination: first means for generating a square wave signal related to the phase encoded input data, second means for generating a crossing pulse signal at a predetermined value of the phase encoded input wave, third means for cyclically counting in a positive and negative sense from a reference level generated clock pulses in response to a first crossing pulse and terminated by a subsequent crossing pulse, count storage means for maintaining an average count of the number of counted clock pulses generated between subsequent pairs of crossing pulses, means for changing the average count in said storage means in accordance with average deviation of the counted clock pulses from the reference level for subsequent periods between crossing pulses, and means for varying the counting characteristics of said third means in accordance with the change in the average count in said storage means.
Claim 10
Dependent Claim
50 words
A digital phase lock system as set forth in claim 7 wherein said third means counts in a positive sense from a zero reference level for an adjustable number of clock pulses and then in a negative sense to the zero reference level and repeats until a subsequent crossing pulse.
Claim 11
Dependent Claim
37 words
A digital phase lock system as set forth in claim 8 wherein said count storage means maintains an average count of the number of counted clock pulses from the zero reference level to the adjustable maximum level.
Claim 12
Dependent Claim
30 words
A digital phase lock system as set forth in claim 9 wherein said means for changing the average count in said storage means varies the maximum positive sense count limit.
Claim 13
Dependent Claim
27 words
A digital phase lock system as set forth in claim 7 including means for resetting said third means to the reference level count between subsequent clock pulses.
Claim 14
Dependent Claim
40 words
A digital phase lock system as set forth in claim 7 wherein said means for changing includes means for storing the deviation of the clock pulses counted by said third means from the reference level at the subsequent crossing pulse.
Claim 15
Dependent Claim
28 words
A digital phase lock system as set forth in claim 12 wherein said means for storing the deviation includes means for dividing the deviation by a preselected factor.
Claim 16
Dependent Claim
31 words
A digital phase lock system as set forth in claim 13 including means for averaging the divided deviation of clock pulses from the reference level for subsequent periods between crossing pulses.
Claim 17
Dependent Claim
31 words
A digital phase lock system as set forth in claim 14 including means responsive to the average deviation to vary the count characteristics when the average deviation exceeds a predetermined limit.
Claim 18
Independent Claim
103 words
A system for decoding phase encoded input data, comprising in combination: first means for generating a square wave signal related to the phase encoded input data, second means responsive to the generated square wave for producing a selected phase signal having a frequency tracking the frequency of the input data, third means receiving and comparing the square wave signal and the selected phase signal and generating a comparison for a preselected relationship therebetween, fourth means for integrating the comparison over a period of the encoded input data, and fifth means responsive to said fourth means to provide recovered data from the encoded input.
Claim 19
Independent Claim
103 words
A system for decoding phase encoded input data, comprising in combination: first means for generating a square wave signal related to the phase encoded input data, second means responsive to the generated square wave for producing a selected phase signal having a frequency tracking the frequency of the input data, third means receiving and comparing the square wave signal and the selected phase signal and generating a comparison for a preselected relationship therebetween, fourth means for integrating the comparison over a period of the encoded input data, and fifth means responsive to said fourth means to provide recovered data from the encoded input.
Claim 20
Dependent Claim
51 words
A system for decoding phase encoded input data as set forth in claim 16 wherein said fifth means generates logic ONE data when the integration of the comparison signal exists at least over 50 percent of an integration period and logic ZERO data when less than 50 percent of a period.
Claim 21
Dependent Claim
109 words
A system for decoding phase encoded input data as set forth in claim 16 wherein said second means includes: means for cyclically counting from a reference level generated clock pulses in response to a first change in direction of the generated square wave and terminated by a subsequent change in direction, count storage means for maintaining an average count of the number of counted clock pulses generated between subsequent changes in direction of the generated square wave, and means for varying the count characteristics of said means for cyclically counting in accordance with the deviation of the counted clock pulses from the reference level exceeding the stored average count.
Claim 22
Dependent Claim
31 words
A system for decoding phase encoded input data as set forth in claim 18 including means responsive to the average count in said storage means for producing the selected phase signal.
Claim 23
Dependent Claim
40 words
A system for decoding phase encoded input data as set forth in claim 18 including means for varying the counting characteristics of said means for cyclically counting in accordance with the change in the average count in said storage means.
Claim 24
Dependent Claim
32 words
A system for decoding phase encoded input data as set forth in claim 18 including means for resetting said means for cyclically counting to the reference level count between subsequent clock pulses.
Claim 25
Dependent Claim
58 words
A system for decoding phase encoded input data as set forth in claim 21 wherein said means for cyclically counting counts from a zero reference level to an adjustable maximum in a positive sense and then in a negative sense to the zero reference level and repeats until a subsequent change in direction of the generated square wave.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-04-22 | 1977-10-22 | 1978-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-04-22 | 1981-10-22 | 1982-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-04-22 | 1985-10-22 | 1986-04-23 | $7700.00 | Window Closed / Lapsed |