Circuit for incrementally phasing digital signals

Claim 2

A circuit for incrementally phasing digital signals connected to an input circuit with a first output indicative of the relative phase of the transmitted timing signal and a second output at the transmitted reference frequency comprising a reversible counter connected to the first output of said input circuit to adjust said reversible counter in accordance with the relative phase of said transmitted timinG signal, an oscillator having its input connected to receive the transmitted reference frequency at the second output of said input circuit, said oscillator having a first output and a second output, complementary to the first output, both outputs being at a frequency greater than said transmitted reference frequency, a first gating network connected to the output of said reversible counter to provide outputs indicative of the relative phase of said transmitted timing signals in accordance with the output of said reversible counter, an output gating network connected to the output of said first gating network, a delay network connected to said output gating network, the output of said output gating network being interconnected as the output of said circuit for incrementally phasing digital signals, and second gating network having its inputs connected to said reversible counter and the first output and second complementary output of said oscillator, the output of said second gating means being connected to said delay network to apply either said output or complementary output of said oscillator, as determined by said reversible counter, to said delay network and said output gating network at a frequency greater than said transmitted reference frequency.

Claim 3

A circuit for incrementally phasing digital signals in accordance with claim 1 wherein said oscillator is a phase locked oscillator which comprises a phase comparator connected to said input circuit, a voltage controlled oscillator connected to the first and second complementary outputs of said phase locked oscillator, and a frequency divider serially connected in an automatic phase control loop with said phase comparator and said voltage controlled oscillator to reduce the frequency output of said voltage controlled oscillator to the frequency of said transmitted reference signal.

Claim 4

A circuit for incrementally phasing digital signals in accordance with claim 2 wherein a second frequency divider is connected between the output of said output gating network and the output of said circuit for incrementally phasing digital signals to divide the frequency output of said output gating network by the ratio of said phase locked oscillator frequency to said transmitted reference frequency.

Claim 5

A circuit for incrementally phasing digital signals in accordance with claim 3 wherein said second gating network comprises first and second AND gates, one input of said first AND gate being connected to the first output of the voltage controlled oscillator of said phase locked oscillator while the other input is connected to said reversible counter, one input of said second AND gate being connected to the second complementary output of the voltage controlled oscillator of said phase locked oscillator while the other input is connected to said reversible counter, and means connecting the outputs of said first and second AND gates to said delay network.

Claim 6

A circuit for incrementally phasing digital signals in accordance with claim 4 wherein said delay network comprises at least an individual logic gate having a propagation delay equivalent to one unit of delay of a duration determined by the desired phasing accuracy for said circuit for incrementally phasing digital signals.

Claim 7

A circuit for incrementally phasing digital signals connected to an input circuit with a first output indicative of the relative phase of the transmitted timing signal and a second output at the transmitted reference frequency, a reversible counter connected to the first output of said input circuit to adjust said reversible counter in accordance with the relative phase of said transmitted timing signal, an oscillator having its input connected to receive the transmitted reference frequency at the second output of said input circuit, said oscillator having a first output and a second output, complementary to the first output, both outputs at a frequency which is a multiple greater than said transmitted reference frequency, a first gating network conneCted to the output of said reversible counter to provide logic level outputs indicative of the relative phase of said transmitted timing signals in accordance with the output of said reversible counter, a plurality of output AND gates each having first and second inputs, the outputs of said plurality of output AND gates being interconnected as the output of said circuit for incrementally phasing digital signals, a plurality of delay networks, means connecting the first input of each of said first plurality of said output AND gates with individual outputs of said first gating network, means connecting each of said plurality of delay networks in a series string with individual delay networks connected between the second inputs of each pair of said plurality of output AND gates, and first and second individual AND gates each having one input connected to said reversible counter, the other input of said first individual AND gate being connected to the first output of said oscillator while the other input of said second individual AND gate is connected to the second complementary output of said oscillator, the outputs of said first and second individual AND gates being connected with said string of said plurality of delay networks such that either said output or said complementary output of said oscillator is applied, as determined by said reversible counter, to said plurality of delay networks and the first AND gate of said plurality of AND gates at a frequency which is a multiple of said transmitted reference.

Claim 8

A circuit for incrementally phasing digital signals connected to an input circuit with a first output indicative of the relative phase of the transmitted timing signal and a second output at the transmitted reference frequency, a reversible counter connected to the first output of said input circuit to adjust said reversible counter in accordance with the relative phase of said transmitted timing signal, an oscillator having its input connected to receive the transmitted reference frequency at the second output of said input circuit, said oscillator having a first output and a second output, complementary to the first output, both outputs at a frequency which is a multiple greater than said transmitted reference frequency, a first gating network conneCted to the output of said reversible counter to provide logic level outputs indicative of the relative phase of said transmitted timing signals in accordance with the output of said reversible counter, a plurality of output AND gates each having first and second inputs, the outputs of said plurality of output AND gates being interconnected as the output of said circuit for incrementally phasing digital signals, a plurality of delay networks, means connecting the first input of each of said first plurality of said output AND gates with individual outputs of said first gating network, means connecting each of said plurality of delay networks in a series string with individual delay networks connected between the second inputs of each pair of said plurality of output AND gates, and first and second individual AND gates each having one input connected to said reversible counter, the other input of said first individual AND gate being connected to the first output of said oscillator while the other input of said second individual AND gate is connected to the second complementary output of said oscillator, the outputs of said first and second individual AND gates being connected with said string of said plurality of delay networks such that either said output or said complementary output of said oscillator is applied, as determined by said reversible counter, to said plurality of delay networks and the first AND gate of said plurality of AND gates at a frequency which is a multiple of said transmitted reference.

Claim 9

A circuit for incrementally phasing digital signals in accordance with claim 6 wherein said oscillator is a phase locked oscillator which comprises a phase comparator connected to said input circuit, a voltage controlled oscillator connected to the first and second complementary outputs of said phase locked oscillator, and a frequency divider serially connected in an automatic phase control loop with said phase comparator and said voltage controlled oscillator to reduce the frequency output of said voltage controlled oscillator to the frequency of said transmitted reference signal.

Claim 10

A circuit for incrementally phasing digital signals in accordance with claim 7 wherein a second frequency divider is connected between the interconnected outputs of said plurality of output AND gates and the output of said circuit for incrementally phasing digital signals to divide the frequency output of said output gating network by the ratio of said phase locked oscillator frequency to said transmitted reference frequency.

Claim 11

A circuit for incrementally phasing digital signals in accordance with claim 8 wherein each of said plurality of delay networks comprises an individual logic gate, each of said individual logic gates having substantially equal propagation delays equivalent to one unit of delay of a duration determined by the desired phasing accuracy.