Patent US3327122A successfully refreshed from Google Patents.
Patent US3806644A successfully refreshed from Google Patents.
US3806644A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video format converter
Assignee: AT&T Inc
•
Filing: 1973-02-23
•
Granted: 1974-04-23
•
Expires: 1993-02-23
Abstract
Abstract Signals having the format standards of the PICTUREPHONE video telephone (PVT) system are converted to a signal having the format standards of commercial television (CTV). Achieving the foregoing is a scan converter which includes two shift registers in which successive lines are alternately stored at the line rate of the PVT system. As one register is filled, samples from the preceding PVT line are read out at a substantially faster rate. The registers are then switched as to function. A signal format is generated to cause the CTV receiver to operate in a noninterlace mode to produce a resulting CTV line raster that is in effect exactly equal to the number of lines in a PVT frame.
Inventors
- 👤 P Browne
- 👤 H Sautter
- 👤 H Burns
- 👤 J Kelly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:58
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/01; H04N7/0105; H04N7/12; H04N7/122
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
164 words
Apparatus for converting a first video signal having a format of the standard specified in TAble I of this specification to a second video signal having a format acceptable by a video receiver designed to receive a signal of the standard specified in TAble II of this specification, comprising: means for receiving said first video signal and for recovering horizontal and vertical sync pulses therefrom; first and second shift registers; means for storing, at an 8 kHz line rate, successive whole lines of said first video signal alternately in said first and second registers; means for reading out, at a 16 kHz line rate, an entire said stored line at a time, from either said register while the other said register is being filled with the next successive said line; means synchronized with said reading out means for applying each said stored line to said video receiver alternately from said registers; and means for causing said video receiver to operate in a noninterlace mode.
Claim 2
Dependent Claim
164 words
Apparatus for converting a first video signal having a format of the standard specified in TAble I of this specification to a second video signal having a format acceptable by a video receiver designed to receive a signal of the standard specified in TAble II of this specification, comprising: means for receiving said first video signal and for recovering horizontal and vertical sync pulses therefrom; first and second shift registers; means for storing, at an 8 kHz line rate, successive whole lines of said first video signal alternately in said first and second registers; means for reading out, at a 16 kHz line rate, an entire said stored line at a time, from either said register while the other said register is being filled with the next successive said line; means synchronized with said reading out means for applying each said stored line to said video receiver alternately from said registers; and means for causing said video receiver to operate in a noninterlace mode.
Claim 3
Dependent Claim
37 words
Apparatus pursuant to claim 1, wherein said causing means comprises means for generating sync pulses to cause the local horizontal oscillator of said video receiver to operate at a rate that produces 534 scan lines per frame.
Claim 4
Dependent Claim
43 words
Apparatus pursuant to claim 1, further comprising: means for generating timing pulses for synchronously sampling the 1 MHz first video signal at a sample rate fs of substantially 2 MHz, said timing pulses being substantially exact multiples of said recovered horizontal sync pulses.
Claim 5
Dependent Claim
58 words
Apparatus pursuant to claim 3, wherein said means for generating timing pulses comprises a phase-locked loop comprising: phase detector means for receiving said recovered horizontal sync pulses, oscillator means operating at a frequency of substantially five times said sample rate fs, and a feedback loop connecting said oscillator means and said detector means, and including frequency divider means.
Claim 6
Dependent Claim
68 words
Apparatus pursuant to claim 4, wherein said first and second shift registers comprise means for storing said samples of said first video signal, and wherein said readout means reads said stored samples out at a rate fo; and means including said timing pulses produced by said phase-locked loop for substantially locking said rate fs and said rate fo to the horizontal line rate of said first video signal.
Claim 7
Dependent Claim
90 words
Apparatus pursuant to claim 5, wherein said detector comprises means for comparing said horizontal sync signal with an 8 kHz signal derived from said oscillator means, thereby to produce a first control signal, and means for receiving from said divider means a 16 kHz signal; and wherein said oscillator means comprises means for conbining said first control signal and said 16 kHz signal to continuously adjust the frequency of said oscillator means thereby to lock said rates fs and fo to said horizontal line rate of said first video signal.
Claim 8
Dependent Claim
65 words
Apparatus pursuant to claim 6, wherein the number of storage elements in each of said storage registers is 210, and wherein the rate fo at which said 210 samples are read from storage in said registers is such that the ratio fo/fs 2.5 is maintained, whereby an aspect ratio of substantially 11:10 is achieved for display of said first video signal on said video receiver.
Claim 9
Dependent Claim
15 words
Apparatus pursuant to claim 6, wherein said first and second shift registers comprise charge-coupled devices.
Claim 10
Dependent Claim
68 words
Apparatus pursuant to claim 6, wherein said reading-out means further comprises: logic unit means having as inputs said first video signal vertical sync pulse and the output of said oscillator means, said logic unit means comprising means for frequency dividing said oscillator means output by 5 and means for frequency dividing said oscillator means output by 2, thereby to produce distinct signals having the frequencies fs and fo.
Claim 11
Dependent Claim
57 words
Apparatus pursuant to claim 9, wherein said logic unit means further comprises: synchronous gate means for combining said vertical sync pulse from said first video signal and said 16 kHz signal from said phase-locked loop to form a composite sync signal; and means including said composite sync signal for alternately leading out said first and second registers.
References Cited (Backward Citations)
US3436474A
Cited
US3621150A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-04-22 | 1977-10-22 | 1978-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-04-22 | 1981-10-22 | 1982-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-04-22 | 1985-10-22 | 1986-04-23 | $7700.00 | Window Closed / Lapsed |