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US3805031A Expired / Lapsed US ⏱️ 0.0 years remaining

Count and store synchronous binary counter

Assignee: United States Department of the Navy
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Filing: 1972-09-25
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Granted: 1974-04-16
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Expires: 1992-09-25
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Abstract

Abstract An improvement in a count and store binary counter system wherein the count is available immediately after the reception of the counting clock pulse. Thus, there is no need to wait for a successive ripple-through, and the possibility of erroneous outputs due to an intermediate ripple-through state is eliminated. The circuitry employed to accomplish the invention includesq among other things, a ripple-through binary counter coupled to an n-bit parallel register.

Inventors

  • 👤 L Leibowitz
  • 👤 R Baldauf
  • 👤 T Street

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 19:53
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/08; H03K21/12; H03K23/00; H03K23/58

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 194 words
A system for counting and storing the number of pulses at an input comprising: a ripple through binary counter connected to said input to count the pulses received; said counter comprising an n-bit ripple through binary counter including a first plurality of flip-flops; storing means connected to said input and to said counter for storing the count in said counter each time a pulse is received; said storing means comprising an n-bit parallel register including a second plurality of flip-flops all connected directly to said input with the output of each of said first plurality of flip-flops connected to the input of one of said second plurality of flip-flops; reset means for introducing a reset pulse into said system, wherein; the reset terminals of all of said second plurality of flipflops and of all of said first plurality of flip-flops except the lowest digit flip-flop are connected to receive said reset pulse; and, the preset terminal of said lowest digit flip-flop is connected to receive said reset pulse, whereby said lowest digit flip-flop is set to logical 1 and all the other flip-flops are set to logical 0 upon receipt of a reset pulse.
Claim 2
Independent Claim 194 words
A system for counting and storing the number of pulses at an input comprising: a ripple through binary counter connected to said input to count the pulses received; said counter comprising an n-bit ripple through binary counter including a first plurality of flip-flops; storing means connected to said input and to said counter for storing the count in said counter each time a pulse is received; said storing means comprising an n-bit parallel register including a second plurality of flip-flops all connected directly to said input with the output of each of said first plurality of flip-flops connected to the input of one of said second plurality of flip-flops; reset means for introducing a reset pulse into said system, wherein; the reset terminals of all of said second plurality of flipflops and of all of said first plurality of flip-flops except the lowest digit flip-flop are connected to receive said reset pulse; and, the preset terminal of said lowest digit flip-flop is connected to receive said reset pulse, whereby said lowest digit flip-flop is set to logical 1 and all the other flip-flops are set to logical 0 upon receipt of a reset pulse.
Claim 3
Dependent Claim 19 words
The system as claimed in claim 1 wherein said first and second plurality of flip-flops are D type flip-flops.

References Cited (Backward Citations)

US3063631A Cited
US3602699A Cited
US3597641A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-04-15 1977-10-15 1978-04-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-04-15 1981-10-15 1982-04-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-04-15 1985-10-15 1986-04-16 $7700.00 Window Closed / Lapsed

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