Device for generating an instruction signal for use in an automatic digital readout apparatus

Claim 1

Device for generating an instruction signal for use in an automatic digital readout apparatus of the measured value relating to the displacement at the measuring point thereof, in which a counting pulse is successively generated each time the displacement exceeds a measuring unit, and the thus-generated pulses are applied to the electronic counter of said apparatus so as to provide the digitally indicated measured value corresponding to the displacement, while the thus-provided digitally indicated measured value is transferred to the memory of said apparatus by means of a detecting pulse generated when the displacement is at said measuring point thereof thereby permitting said digitally indicated measured value at said measuring point to be stored in said memory, wherein the improvement comprises a separate readout signal circuit adapted to receive said counting pulses so as to provide the instruction signal for demanding said digitally indicated measured value to be transferred from said electronic counter to said memory, said readout signal circuit including at least one circuit element for delaying the transfer of the counting pulse received by said readout signal circuit after the same receives said detecting pulse by a time period longer than the interference period in said electronic counter in which period the correct digitally indicated measured value cannot be obtained due to the counting operation in said electronic counter, thereby permitting said instruction signal to be provided after said interference period elapses, and wherein said readout signal circuit comprises a flip-flop circuit and an AND circuit, so that said detecting pulse is applied to said flip-flop circuit to thereby invert the operating condition thereof, and the output of said flip-flop circuit and said counting pulses are applied to said AND circuit, at least one delay element being provided in the line in said readout signal circuit transmitting said counting pulses through said AND circuit, the total delay time of said at least one delay element being greater than said interference period, tHe output of said interference period, the output of said AND circuit being lead back to said flip-flop circuit to thereby reset the same.