Multiple-phase control signal generator

Claim 2

Apparatus for generating multiple-phase control signals comprising: a plurality of bistable means connected into a closed cascade, each bistable means having first and second input means and first and second output means representative of the logic state and the complement of the logic state of the bistable means; a first plurality of switches, separate ones coupling signals representative of the logic state of each bistable means to an input of the succeeding bistable means; a second plurality of switches, separate ones coupling signals representative of the complement of the logic state of each bistable means to the other input of the succeeding bistable means; means for receiving a one-phase clock signal from an independent source; and means for maintaining conductive the switches of the first plurality in response only to a pulse in the clock signal and for maintaining conductive the switches of the second plurality in response only to the absence of a pulse in the clock signal.

Claim 3

Apparatus as recited in claim 1 wherein: the first and second input means included in each bistable means are, respectively, set and reset input means; the switches of the second plurality are coupled to the set inputs of the bistable means; and the switches of the first plurality are coupled to the reset inputs of the bistable means.

Claim 4

Apparatus as recited in claim 1 wherein the means for receiving the one-phase clock signals includes: a first conduction path coupled to the switches of the first plurality; a second conduction path coupled to the switches of the second plurality; and logically inverting means coupled betweeN the first and second conduction paths.

Claim 5

Apparatus as recited in claim 3 wherein: the switches of the first plurality include logic gates each having a first input coupled to an output means of a preceding bistable means, a second input means coupled to the first conduction path, and an output means coupled to an input means of a succeeding bistable means in the cascade; and the switches of the second plurality include logic gates each having a first input coupled to the other output means of the preceding bistable means, a second input coupled to the second conduction path, and an output coupled to the other input means of the succeeding bistable means in the cascade.

Claim 6

Apparatus as recited in claim 4 wherein the logic gates in the switches of the first and second pluralities are logically inverting; and the first and second input means included in each bistable means are, respectively, set and reset input means.

Claim 7

Apparatus as recited in claim 5 wherein: separate ones of the first plurality of logic gates are connected between the second output means of a preceding bistable means and the reset input means of a succeeding bistable means; and separate ones of the second plurality of logic gates are connected between the first output means of the preceding bistable means and the set input means of the succeeding bistable means.

Claim 8

Apparatus for generating multiple-phase control signals comprising: a cascaded plurality of bistable means connected into a closed cascade, each bistable means having set and reset input means for selectively setting and resetting the state thereof, and each bistable means additionally having first and second output means representative of the logic state and the complement of the logic state of the bistable means; first and second pluralities of switches, separate ones of said pluralities coupling an output of one bistable means to an input of the succeeding bistable means in the cascade; separate ones of the switches of the first plurality coupling the complement of the logic state of each bistable means to the set input means of the succeeding bistable means in the cascade; separate ones of the switches of the second plurality coupling the logic state of each bistable means to the reset input of the succeeding bistable means in the cascade; means for receiving a one-phase clock signal from an independent source and for generating the logical complement of said clock signal; means coupling the clock signal in common to the first plurality of switches and responsive to pulses in the clock signal for simultaneously closing the switches of the first plurality; and means coupling the complement of the clock signal in common to the second plurality of switches and responsive to the pulses in the complement of the clock signal for simultaneously closing said switches of the second plurality.

Claim 9

Apparatus for generating multiple-phase control signals comprising: a cascaded plurality of bistable means connected into a closed cascade, each bistable means having set and reset input means for selectively setting and resetting the state thereof, and each bistable means additionally having first and second output means representative of the logic state and the complement of the logic state of the bistable means; first and second pluralities of switches, separate ones of said pluralities coupling an output of one bistable means to an input of the succeeding bistable means in the cascade; separate ones of the switches of the first plurality coupling the complement of the logic state of each bistable means to the set input means of the succeeding bistable means in the cascade; separate ones of the switches of the second plurality coupling the logic state of each bistable means to the reset input of the succeeding bistable means in the cascade; means for receiving a one-phase clock signal from an independent source and for generating the logical complement of said clock signal; means coupling the clock signal in common to the first plurality of switches and responsive to pulses in the clock signal for simultaneously closing the switches of the first plurality; and means coupling the complement of the clock signal in common to the second plurality of switches and responsive to the pulses in the complement of the clock signal for simultaneously closing said switches of the second plurality.

Claim 10

Apparatus as recited in claim 7 wherein: the plurality of bistable means includes first, second, and third bistable means; the first plurality of switches includes three switches; and the second plurality of switches includes three switches; and the apparatus further includes feedback means adapted to prevent the first bistable means from changing state upon arrival of a clock pulse if at that time a ''''zero'''' is stored in the third bistable means.