Patent US3800412A successfully refreshed from Google Patents.
US3800412A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for producing surface-oriented semiconducting devices
Assignee: Skyworks Solutions Inc
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Filing: 1972-04-05
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Granted: 1974-04-02
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Expires: 1992-04-05
Abstract
Abstract Surface-oriented diodes are produced by forming respective window areas for N+ and P+ doping in the surface of a semiconductive substrate, the first and second window areas being separated by a coating spacing pattern of uniform width. Diffusion of dopants into the N+ and P+ windows is carried out alternately for the respective window areas with the other window area masked. Similarly, the formation of ohmic contacts may be carried out alternately for the respective window areas, with the other window area masked. The process enables production of surface-oriented diodes on an economically feasible scale, while being tolerant of the realistic limits of photo-alignment precision and registration capabilities of the microcircuit art.
Inventors
- 👤 E Wall
- 👤 W Niblack
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:32
CPC Classifications
H; H10; H10P; H10P95/00; H10D; H10D84/00; H10D84/01; H10D84/201; H10D84/204; H10D84/221; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/028
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
266 words
Process for preparing surface-oriented semiconductive devices of the type having closely spaced surface regions of different conductivities on a semiconductive substrate separated by a line width of 0.1 to 1.0 mils at said surface with improved uniformity of such line width comprising the steps of, coating a semiconductive substrate with a first diffusion barrier layer, overcoating said layer with an overlay coating of a refractory material, and overcoating the refractory overlay coating with an etchable second diffusion barrier, forming a window-defining spacing pattern at the outer surface of said first diffusion barrier in the form of a narrow surface band to define adjacent first and second window areas on opposite sides of said band with the band having a different etch resistance characteristic relative to said adjacent first and second window surface areas, the so formed window surface areas retaining only said first diffusion barrier layer and having boundaries defined by the refractory layer of said band, forming a mask over a first one of said first and second window areas, said masking having a boundary extending into the surface are of said spacing pattern while leaving the second of said first and second window areas unmasked, etching the semiconductive substrate with an etchant which is blocked by said mask and spacing pattern to effectively etch the first diffusion barrier layer from said second one of said window areas, altering the conductivity of said substrate in a limited depth surface layer thereof located at said second window area, removing said mask, and applying first and second spaced contacts to said first and second window areas respectively.
Claim 2
Dependent Claim
266 words
Process for preparing surface-oriented semiconductive devices of the type having closely spaced surface regions of different conductivities on a semiconductive substrate separated by a line width of 0.1 to 1.0 mils at said surface with improved uniformity of such line width comprising the steps of, coating a semiconductive substrate with a first diffusion barrier layer, overcoating said layer with an overlay coating of a refractory material, and overcoating the refractory overlay coating with an etchable second diffusion barrier, forming a window-defining spacing pattern at the outer surface of said first diffusion barrier in the form of a narrow surface band to define adjacent first and second window areas on opposite sides of said band with the band having a different etch resistance characteristic relative to said adjacent first and second window surface areas, the so formed window surface areas retaining only said first diffusion barrier layer and having boundaries defined by the refractory layer of said band, forming a mask over a first one of said first and second window areas, said masking having a boundary extending into the surface are of said spacing pattern while leaving the second of said first and second window areas unmasked, etching the semiconductive substrate with an etchant which is blocked by said mask and spacing pattern to effectively etch the first diffusion barrier layer from said second one of said window areas, altering the conductivity of said substrate in a limited depth surface layer thereof located at said second window area, removing said mask, and applying first and second spaced contacts to said first and second window areas respectively.
Claim 3
Dependent Claim
36 words
Process in accordance with claim 1 wherein, said electrical contact applying step comprises the formation of ohmic contacts at said window areas to form at least one diode device at the surface of said semiconductive substrate.
Claim 4
Dependent Claim
28 words
Process in accordance with claim 1 wherein, each of said first and second window areas is subjected to a conductivity altering process to form a P-I-N semiconductive device.
Claim 5
Dependent Claim
37 words
Process in accordance with claim 1 wherein, each of said first and second window areas is subjected to said masking forming and said conductivity altering steps in alternating time sequence with the other of said window areas.
Claim 6
Dependent Claim
50 words
Process in accordance with claim 1 wherein, said electrical contact applying step comprises, alternately masking each one of said window areas with a mask having a boundary extending into the surface area of said narrow band spacing pattern and applying a contact material to the other of said window areas.
Claim 7
Dependent Claim
18 words
Process in accordance with claim 1 wherein a plurality of said devices are formed in a single substrate.
Claim 8
Dependent Claim
17 words
Process in accordance with claim 6 wherein said window-spacing surface pattern is formed as a cross-hatched grid.
Claim 9
Dependent Claim
35 words
Process in accordance with claim 1 comprising the further and subsequent steps of building said contacts to self-supporting size and removing said substrate from the devices to form a beam lead construction of said device.
Claim 10
Dependent Claim
33 words
Process in accordance with claim 1 wherein said first diffusion barrier is a thermal oxide of the substrate material and the second diffusion barrier is a pyrolytically deposited oxide of the substrate material.
Claim 11
Dependent Claim
28 words
Process in accordance with claim 1 wherein said substrate material is silicon, said first and second diffusion barriers are silicon dioxide and said refractory material is silicon nitride.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-04-01 | 1977-10-01 | 1978-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-04-01 | 1981-10-01 | 1982-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-04-01 | 1985-10-01 | 1986-04-02 | $7700.00 | Window Closed / Lapsed |