Time division communication system

Claim 2

In a time division communication system wherein a plurality of time slots occurs in repetitive cycles, a circuit for coupling signals between an incoming time division bus, an outgoing time division bus and a communication path comprising apparatus operative in a distinct time slot including means for receiving an outgoing signal from said communication path, first means for storing said received outgoing signal, means for applying said stored outgoing signal to said outgoing time division bus, means for coupling said outgoing time division bus to said incoming time division bus, means for receiving the signal appearing on said incoming time division bus, means responsive to said received incoming signal and said stored outgoing signal for generating a signal corresponding to the difference between the received incoming signal and the stored outgoing signal from said first storing means, and second means for storing said generated signal, and apparatus operative in the time interval between successively occurring distinct time slots comprising means responsive to said stored generated signal for producing and applying a distinct signal to said first storing means and means for applying the signal in said first storing means to said communication path.

Claim 3

In a time division communication system wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 1 wherein said second storing means comprises second and third storage devices, said signal generating means comprises amplifying means having first and second inputs and first and second outputs, means for applying said stored outgoing signal to said first input, means for applying said received incoming signal to said second input, said amplifying means being operative in said distinct time slot to produce a first signal corresponding to said received incoming signal less said stored outgoing signal on said first output and to produce a second signal corresponding to said stored outgoing signal less said received incoming signal on said second output, means for applying said first signal to said second storage device and means for applying said second signal to said third storage device, and wherein said distinct signal producing and applying means comprises means responsive to said stored first signal for producing and applying a third signal to said first storing means, and means responsive to said stored second signal for producing and applying a fourth signal to said first storing means.

Claim 4

In a time division communication system wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 2 wherein said first signal applying means comprises switching means connected between said first output and said second storage device opErative in said distinct time slot for connecting said first output to said second storage device, and said second signal applying means comprises switching means connected between said second output and said third storage device operative in said distinct time slot for connecting said second output to said third storage device.

Claim 5

In a time division communication system wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 3 wherein said third signal producing and applying means comprises first type current generating means and said fourth signal producing and applying means comprises second type current generating means.

Claim 6

In a time division communication system wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 4 wherein said first storing means comprises a first storage capacitor, said second storage device comprises a second storage capacitor and said third storage device comprises a third storage capacitor.

Claim 7

In a time division communication system wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 5, wherein said first type generating means comprises a positive current generating circuit and said second type generating means comprises a negative current generating circuit.

Claim 8

A time division communication system wherein a plurality of time slots occurs in repetitive cycles comprising a plurality of communication path storage devices, first and second common buses, a control signal source, each storage device having an associated circuit comprising means responsive to a control signal from said source for applying a signal from said path storage device to said first common bus, means for receiving a signal from said second common bus, means connected to said receiving means and to said storage device responsive to said control signal for generating a signal corresponding to the difference between said received signal and said storage device signal, means connected to said generating means responsive to said control signal for storing said generated signal, means connected between said storing means and said storage device responsive to said stored generated signal in the time interval between successive distinct time slots for producing and applying a distinct signal to said storage device, and means for exchanging signals among a plurality of selected storage device circuits in a distinct time slot comprising means for applying said control signal to each selected storage device circuit in said distinct time slot, means responsive to the selected storage device signals applied to said first common bus in said distinct time slot for producing a signal corresponding to the sum of said applied selected storage device signals, and means for applying said produced signal to said second common bus in said distinct time slot.

Claim 9

A time division communication system wherein a plurality of time slots occurs in repetitive cycles comprising a plurality of communication path storage devices, first and second common buses, a control signal source, each storage device having an associated circuit comprising means responsive to a control signal from said source for applying a signal from said path storage device to said first common bus, means for receiving a signal from said second common bus, means connected to said receiving means and to said storage device responsive to said control signal for generating a signal corresponding to the difference between said received signal and said storage device signal, means connected to said generating means responsive to said control signal for storing said generated signal, means connected between said storing means and said storage device responsive to said stored generated signal in the time interval between successive distinct time slots for producing and applying a distinct signal to said storage device, and means for exchanging signals among a plurality of selected storage device circuits in a distinct time slot comprising means for applying said control signal to each selected storage device circuit in said distinct time slot, means responsive to the selected storage device signals applied to said first common bus in said distinct time slot for producing a signal corresponding to the sum of said applied selected storage device signals, and means for applying said produced signal to said second common bus in said distinct time slot.

Claim 10

A time division communication system wherein a plurality of time slots occurs in repetitive cycles according to claim 7, wherein said control signal source comprises a control circuit for producing control codes, a plurality of registers each register being connected to one associated circuit and each register comprising means for receiving a control code corresponding to a selected call connection in a distinct time slot from said control circuit, means for storing said control code and means responsive to said stored control code for generating and applying a control signal to said connected circuit in said distinct time slot of each repetitive cycle, and said system further comprising means for identifying an idle time slot including a third common bus, means connected between each register and said third common bus for applying the control signal in each register to said third common bus in the time slot of one repetitive cycle, and means for detecting the nonappearance of any control signal in a particular time slot, and said control circuit further comprising means responsive to the operation of said detecting means For storing a control code designating said particular time slot as an idle time slot.

Claim 11

A time division communication system wherein a plurality of time slots occurs in repetitive cycles according to claim 7, wherein said control signal source comprises a control circuit for producing control codes, a plurality of registers, each register being connected to one associated circuit and each register comprising means for receiving a control code corresponding to a selected call connection in a distinct time slot from said control circuit, means for storing said control code and means responsive to said stored control code for generating and applying a control signal to said connected circuit in said distinct time slot of each repetitive cycle, and said system further comprising means for adding a communication path storage device to a selected call connection comprising a third common bus, means for applying the control signal from one already selected associated circuit register to said third common bus in said distinct time slot, means connected to said third common bus for detecting the occurrence of the control signal in said already selected associated register in said distinct time slot, and said control circuit further comprising means responsive to the operation of said detecting means in said distinct time slot for applying a control code to the added communication path storage device associated circuit register in said distinct time slot.

Claim 12

A time division communication system wherein a plurality of time slots occurs in repetitive cycles according to claim 7 wherein said storing means comprises second and third stores said signal generating means comprises amplifying means having first and second inputs and first and second outputs, means for applying the signal in said path storage device to said first input, means for applying the signal received from said second bus to said second input, said amplifying means being operative responsive to said control signal to produce a first signal corresponding to said received second bus signal less said path storage device signal on said first output and to produce a second signal corresponding to said path storage device signal less said received second bus signal on said second output, means for applying said first signal to said second store and means for applying said second signal to said third store, and wherein said distinct signal producing and applying means comprises means responsive to said stored first signal for producing and applying a third signal to said path storage device and means responsive to said stored second signal for producing and applying a fourth signal to said path storage device.

Claim 13

In a time division communication system wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 10 wherein said first signal applying means comprises switching means connected between said first output and said second store responsive to said control signal for connecting said first output to said second store and said second signal applying means comprises switching means connected between said second output and said third store responsive to said control signal for connecting said second output to said third store.

Claim 14

In a time division communication system wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 11 wherein said third signal producing and applying means comprises first type current generating means and said fourth signal producing and applying means comprises second type current generating means.

Claim 15

In a time division communication system wherein a plurality of time slots occurs in repetitive cycles, a circuit according to claim 12 wherein said path storage device comprises a first storage capacitor, said second store comprises a second storage capacitor and said third store comprises a third storage capacitor.

Claim 16

In a time division communication system wherein a plurality of time slots occurs in repetitiVe cycles, a circuit according to claim 13, wherein said first type generating means comprises a positive current generating circuit and said second type generating means comprises a negative current generating circuit.

Claim 17

A time division communication system wherein a plurality of time slots occurs in repetitive cycles comprising a plurality of communication paths, first and second common buses and a control signal source, each communication path having an associated circuit coupled to said communication path including a first storage capacitor, means for applying an outgoing signal from the coupled communication path to said first storage capacitor, means responsive to said control signal for applying said stored outgoing signal from said first storage capacitor to said first common bus, means for receiving a signal from said second common bus, a difference amplifier having first and second inputs and first and second outputs, means for applying said received second bus signal to said first input, means for applying said stored outgoing signal to said second input, said difference amplifer being responsive to said control signal to produce a first signal corresponding to said received second bus signal less said stored outgoing signal on said first output and to produce a second signal corresponding to said outgoing signal less said received second bus signal on said second output, second and third storage capacitors, first switching means responsive to said control signal for applying said first signal to said second storage capacitor, second switching means responsive to said control signal for applying said second signal to said third storage capacitor, means connected from said second storage capacitor to said first storage capacitor responsive to said first signal stored in said second storage capacitor for generating and applying a positive current to said first storage capacitor, means connected from said third storage capacitor to said first storage capacitor responsive to the second signal stored in said third storage capacitor for generating and applying a negative current to said first storage capacitor, and means for exchanging signals amoung selected communication path circuits in a distinct time slot comprising means for applying said control signal to each of a plurality of selected communication path circuits in said distinct time slot, and a circuit connected from said first common bus to said second common bus for summing the stored outgoing communication path signals appearing on said first common bus in said distinct time slot and for applying the resultant sum signal to said second common bus.

Claim 18

A time division communication system wherein a plurality of time slots occurs in repetitive cycles comprising a plurality of communication paths, first and second common buses and a control signal source, each communication path having an associated circuit coupled to said communication path including a first storage capacitor, means for applying an outgoing signal from the coupled communication path to said first storage capacitor, means responsive to said control signal for applying said stored outgoing signal from said first storage capacitor to said first common bus, means for receiving a signal from said second common bus, a difference amplifier having first and second inputs and first and second outputs, means for applying said received second bus signal to said first input, means for applying said stored outgoing signal to said second input, said difference amplifer being responsive to said control signal to produce a first signal corresponding to said received second bus signal less said stored outgoing signal on said first output and to produce a second signal corresponding to said outgoing signal less said received second bus signal on said second output, second and third storage capacitors, first switching means responsive to said control signal for applying said first signal to said second storage capacitor, second switching means responsive to said control signal for applying said second signal to said third storage capacitor, means connected from said second storage capacitor to said first storage capacitor responsive to said first signal stored in said second storage capacitor for generating and applying a positive current to said first storage capacitor, means connected from said third storage capacitor to said first storage capacitor responsive to the second signal stored in said third storage capacitor for generating and applying a negative current to said first storage capacitor, and means for exchanging signals amoung selected communication path circuits in a distinct time slot comprising means for applying said control signal to each of a plurality of selected communication path circuits in said distinct time slot, and a circuit connected from said first common bus to said second common bus for summing the stored outgoing communication path signals appearing on said first common bus in said distinct time slot and for applying the resultant sum signal to said second common bus.

Claim 19

A time division communication system wherein a plurality of time slots occurs in repetitive cycles according to claim 15 wherein each of said first, second and third storage capacitors has first and second terminals, said first switching means comprises a first diode having an anode and a cathode, said first diode anode being connected to the first terminal of said second storage capacitor, said first diode cathode being connected to said first output, said second switching means comprising a transistor having collector, emitter and base electrodes and a second diode having an anode and a cathode, said base electrode being connected to said second output, said collector electrode being connected to the anode of said second diode and the cathode of said second diode being connected to the first terminal of said third storage capacitor.

Claim 20

A time division communication system wherein a plurality of time slots occurs in repetitive cycles according to claim 16 wherein each of said positive and negative current generating means has an input and output, said positive generating means input being connected to the first terminal of said second storage capacitor, said negative current generating means input being connected to the first terminal of said third storage capacitor, and the outputs of said positive and negative current generation means being both connecTed to the first terminal of said first storage capacitor.

Claim 21

A time division communication system wherein a plurality of time slots occurs in repetitive cycles according to claim 17 wherein said difference amplifier further comprises a third input and means for applying said control signal to said third input in said distinct time slot, said first and second diodes being rendered conductive in response to the control signal applied to said difference amplifier third input.

Claim 22

A time division communication system wherein a plurality of time slots occurs in repetitive cycles according to claim 18 wherein said means for applying the stored outgoing signal to said first common bus comprises bidirectional switching means having first, second and third electrodes and impedance means having first and second terminals, said switching means first electrode being connected to said first storage capacitor first terminal, said switching means third electrode being connected to said impedance means first terminal, means for applying said control signal to said switching means second electrode, and said impedance means second terminal being connected to said first common bus.