US3795822A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiemitter coupled logic gate
Assignee: HP Inc
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Filing: 1972-08-14
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Granted: 1974-03-05
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Expires: 1992-08-14
Abstract
Abstract The emitters and bases of two transistors, at least one of which has more than one emitter, are used as inputs, while the collectors and emitters are used as outputs. The collector of the first transistor is connected to the base of the second transistor. The collectors of both transistors are electrically biased. A resistor is connected between the bias source and the collector of the first transistor. A third transistor, connected as a diode, clamps the voltage across the resistor to a selected value even if more than one input to the first transistor is low. With changes in inputs and outputs, the circuit can function as a basic AND-OR gate, a trigger circuit for pulse shaping, an R-S latch, and a gated latch. By combination of basic gates, more complex logic functions can be achieved.
Inventors
- 👤 Z Skokan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0863
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
255 words
A gating circuit comprising: a. first gain element having an input circuit and an output circuit, the input circuit having a base electrode and a plurality of emitter electrodes common to the input circuit and the output circuit, the output circuit including a collector electrode and said plurality of emitter electrodes; a second gain element having an input circuit and an output circuit, the input circuit having a base electrode and at least one emitter electrode means common to the input circuit and the output circuit, the output circuit including a collector electrode and said emitter electrode; means operatively connecting the collector electrode of the first gain element to the base electrode of the second gain element; bias means connected to the electrodes of the first and second gain elements for supplying bias signals to the first gain element for operation thereof in common base configuration and for supplying bias signals to the second gain element for operation thereof in the common collector configuration; first circuit means connected to the collector electrode of the first gain element for limiting the level of bias signal thereon substantially independent of input signals applied to the emitter electrodes of the first gain element; second circuit means connected to selected ones of the emitter electrodes of the first gain element for applying input signals thereto; and means connected to an emitter electrode of the second gain element for providing an output signal representative of a logic combination of signals applied to the emitter electrodes of the first gain element.
Claim 2
Dependent Claim
255 words
A gating circuit comprising: a. first gain element having an input circuit and an output circuit, the input circuit having a base electrode and a plurality of emitter electrodes common to the input circuit and the output circuit, the output circuit including a collector electrode and said plurality of emitter electrodes; a second gain element having an input circuit and an output circuit, the input circuit having a base electrode and at least one emitter electrode means common to the input circuit and the output circuit, the output circuit including a collector electrode and said emitter electrode; means operatively connecting the collector electrode of the first gain element to the base electrode of the second gain element; bias means connected to the electrodes of the first and second gain elements for supplying bias signals to the first gain element for operation thereof in common base configuration and for supplying bias signals to the second gain element for operation thereof in the common collector configuration; first circuit means connected to the collector electrode of the first gain element for limiting the level of bias signal thereon substantially independent of input signals applied to the emitter electrodes of the first gain element; second circuit means connected to selected ones of the emitter electrodes of the first gain element for applying input signals thereto; and means connected to an emitter electrode of the second gain element for providing an output signal representative of a logic combination of signals applied to the emitter electrodes of the first gain element.
Claim 3
Dependent Claim
28 words
A gating circuit as in claim 1 wherein a unidirectionally conducting element is connected to the collector electrode of the first gain element to prevent the saturation thereof.
Claim 4
Dependent Claim
78 words
A gating circuit as in claim 1 wherein: the second gain element includes first and Second emitter electrodes; and comprising: means connected to one of the emitter electrodes of the second gain element for applying signal thereon to one of the emitter electrodes of the first gain element for producing an output on another emitter electrode of the second gain element which is a logic combination of signals applied to the emitter electrodes of the first gain element.
Claim 5
Dependent Claim
50 words
A gating circuit as in claim 1 wherein said bias means includes a resistive element connected between each of the emitter electrodes of the first gain element and a source of bias signal of greater magnitude than the bias signal appearing on the base electrode of said first gain element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-04 | 1977-09-03 | 1978-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-04 | 1981-09-03 | 1982-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-04 | 1985-09-03 | 1986-03-05 | $7700.00 | Window Closed / Lapsed |