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US3793631A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital computer apparatus operative with jump instructions

Assignee: Westinghouse Electric Corp
•
Filing: 1972-09-22
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Granted: 1974-02-19
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Expires: 1992-09-22
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Abstract

Abstract Disclosed is a digital computer system including a programmed microprocessor system of the type used in real time systems, in industrial process control and in small scale data processing. The system can be extended and reduced in processing capabilities and in memory capabilities without any change in the data buses and the control line buses thereof, and without internal changes in the units which are added or removed. In particular, the system may include a basic microprocessor system having a basic macroprocessor, a small number of registers and a read-only memory, or it may be extended by adding, in succession, an extended processor and a read-write memory, a direct memory access unit, additional memories, and a maintenance panel which can monitor or control any system functions which can be monitored or controlled by the basic or extended microprocessors. Any of the units other than the basic system can be removed or added at any time, by plugging and unplugging, to change the size and capabilities of the system to suit particular needs. Microprocessor speed is optimized by allowing for overlap of microprocessor functions, such as overlap between instruction execution and instruction fetch, and between writing the result of the current instruction while decoding the next instruction. Timing in the system is fast pipeline timing without artificial delays. The system provides a diversified set of instructions, and particularly bit manipulation instructions in what is basically a byte oriented machine. A designator register is provided for increasing instruction diversity. The system organization allows the full instruction set of the system to be operable on input/output hardware connected to the system through regular system registers and is thus particularly suitable for industrial process control applications, and for other monitoring and control applications.

Inventors

  • 👤 S Silverstein
  • 👤 K Daggett

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 16:52
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3842

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 124 words
Digital computer apparatus comprising a basic processor system including an addressable memory for storing instructions and for reading out selected stored instructions from addressed memory locations; a processor having an instruction register operative with said memory for receiving therefrom and for storing instructions, said processor including means for performing jump instructions in which a jump is taken from a current instruction to a nonsequential next instruction and including means for initiating the fetch from memory of the next sequential instruction while said processor determines if said current instruction is a jump instruction, and means for aborting the fetch of said next sequential instruction when said processor does respond to a jump instruction and for initiating the fetch from memory of said nonsequential next instruction.
Claim 2
Dependent Claim 124 words
Digital computer apparatus comprising a basic processor system including an addressable memory for storing instructions and for reading out selected stored instructions from addressed memory locations; a processor having an instruction register operative with said memory for receiving therefrom and for storing instructions, said processor including means for performing jump instructions in which a jump is taken from a current instruction to a nonsequential next instruction and including means for initiating the fetch from memory of the next sequential instruction while said processor determines if said current instruction is a jump instruction, and means for aborting the fetch of said next sequential instruction when said processor does respond to a jump instruction and for initiating the fetch from memory of said nonsequential next instruction.
Claim 3
Dependent Claim 49 words
The digital computer apparatus of claim 1 including a program counter operative to cause the memory to read out a new instruction during the execution of a current instruction, thereby providing for overlap between the execution of one instruction and the reading out of another instruction from the memory.
Claim 4
Dependent Claim 57 words
The digital computer apparatus of claim 2 including timing, control and decoding means for causing writing the result of a current instruction into a selected addressable register while decoding the operation code of another instruction, thereby providing for time overlap between the storing of the result of a current instruction and the decoding of the next instruction.
Claim 5
Dependent Claim 49 words
The digital computer apparatus of claim 1, with said memory having a cycle comprising a read part and a restore part, and with said means for aborting the fetch of the next sequential instruction being operative during the restore part of said cycle if the jump instruction is provided.
Claim 6
Dependent Claim 90 words
The digital computer apparatus of claim 1, with said memory having a cycle of operation comprising a read out part and a restore part, with said means for initiating the fetch from memory of the next sequential instruction being operative in relation to said read part of said cycle while the processor determines that a jump instruction has been provided, and with said means for aborting the fetch of the next sequential instruction being operative in relation to the restore part of said cycle when the jump instruction is provided.
Claim 7
Dependent Claim 79 words
The digital computer apparatus of claim 1, with said means for initiating the fetch from memory of the next sequential instruction being operative while said processor determines if the current instruction is a jump instruction, and with said means for aborting the fetch of said next sequential instruction being operative in relation to the normal operating cycle of the processor such that when a jump is not to be taken the accessing of the next sequential instruction takes place.
Claim 8
Dependent Claim 36 words
The digiTal computer apparatus of claim 1, including a program counter operative with the memory to read out a new instruction during the execution of the current instruction to reduce the time required for such operations.
Claim 9
Dependent Claim 55 words
The digital computer apparatus of claim 3, with said selected addressable register being specified by the current instruction while decoding the operation code and source register address of the next instruction thereby providing for time overlap between writing the result of a current instruction into said addressable register and the decoding of the next instruction.

References Cited (Backward Citations)

US3570006A Cited
US3551895A Cited
US3559183A Cited
US3614747A Cited
US3573854A Cited
US3553655A Cited
US3713108A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-02-18 1977-08-20 1978-02-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-02-18 1981-08-20 1982-02-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-02-18 1985-08-20 1986-02-19 $7700.00 Window Closed / Lapsed

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