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US3790894A Expired / Lapsed US ⏱️ 0.0 years remaining

Binary shaping circuit

Assignee: Fujitsu Ltd
•
Filing: 1971-12-23
•
Granted: 1974-02-05
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Expires: 1991-12-23
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Abstract

Abstract A level setting circuit changes the level of the input signals to a predetermined reference level when the input signals exceed the reference level. A comparator is connected to the level setting circuit and to the input for comparing the input signals with the signals having the reference level produced by the level setting circuit. The comparator produces an output corresponding to the difference in level between the input signals and the reference level. A binary circuit connected to the comparator produces a pulse when the output of the comparator exceeds a predetermined level.

Inventors

  • 👤 Y Iizuka
  • 👤 T Morita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 13:22
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/403; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 119 words
A binary shaping circuit, comprising input means for supplying input signals; delay circuit means connected to the input means for delaying the input signals; level setting circuit means connected to the delay circuit means for changing the level of said delayed signals to a predetermined reference level when said delayed signals exceed the reference level; comparator means connected to the level setting circuit means and to the input means for comparing the input signals and said changed signals and for producing the output signals corresponding to the difference in level between the input signals and said changed signals; and binary circuit means connected to the comparator means for producing a pulse when said output signals exceeds a predetermined level.
Claim 2
Dependent Claim 119 words
A binary shaping circuit, comprising input means for supplying input signals; delay circuit means connected to the input means for delaying the input signals; level setting circuit means connected to the delay circuit means for changing the level of said delayed signals to a predetermined reference level when said delayed signals exceed the reference level; comparator means connected to the level setting circuit means and to the input means for comparing the input signals and said changed signals and for producing the output signals corresponding to the difference in level between the input signals and said changed signals; and binary circuit means connected to the comparator means for producing a pulse when said output signals exceeds a predetermined level.
Claim 3
Dependent Claim 119 words
A binary shaping circuit, comprising input means for supplying input signals; level setting circuit means connected to the input means for changing the level of the input signals to a predetermined reference level when the input signals exceed the reference level; delay circuit means connected to the level setting circuit means for delaying said changed signals; comparator means connected to the delay circuit means and to the input means for comparing the input signals and said delayed signals and for producing the output signals corresponding to the difference in level between the inpul signals and said delayed signals; and binary circuit means connected to the comparator means for producing a pulse when said output signals exceeds a predetermined level.
Claim 4
Dependent Claim 119 words
A binary shaping circuit, comprising input means for supplying input signals; level setting circuit means connected to the input means for changing the level of the input signals to a predetermined reference level when the input signals exceed the reference level; delay circuit means connected to the level setting circuit means for delaying said changed signals; comparator means connected to the delay circuit means and to the input means for comparing the input signals and said delayed signals and for producing the output signals corresponding to the difference in level between the inpul signals and said delayed signals; and binary circuit means connected to the comparator means for producing a pulse when said output signals exceeds a predetermined level.
Claim 5
Dependent Claim 119 words
A binary shaping circuit, comprising input means for supplying input signals; delay circuit means connected to the input means for delaying the input signals; level setting circuit means connected to the input means for changing the level of the input signals to a predetermined reference level when the input signals exceed the reference level; comparator means connected to the delay circuit means and to the level setting circuit means for comparing said delayed signals and said changed signals and for producing the output signals corresponding to the difference in level between said delayed signals and said changed signals; and binary circuit means connected to the comparator means for producing a pulse when said output signals exceeds a predetermined level.
Claim 6
Dependent Claim 119 words
A binary shaping circuit, comprising input means for supplying input signals; delay circuit means connected to the input means for delaying the input signals; level setting circuit means connected to the input means for changing the level of the input signals to a predetermined reference level when the input signals exceed the reference level; comparator means connected to the delay circuit means and to the level setting circuit means for comparing said delayed signals and said changed signals and for producing the output signals corresponding to the difference in level between said delayed signals and said changed signals; and binary circuit means connected to the comparator means for producing a pulse when said output signals exceeds a predetermined level.

References Cited (Backward Citations)

US3070779A Cited
US3076145A Cited
US3130371A Cited
US3293553A Cited
US3334298A Cited
US3489921A Cited
US3532905A Cited
US3509279A Cited
US3584310A Cited
US3594649A Cited
US3638183A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-02-04 1977-08-06 1978-02-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-02-04 1981-08-06 1982-02-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-02-04 1985-08-06 1986-02-05 $7700.00 Window Closed / Lapsed

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