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US3790885A Expired / Lapsed US ⏱️ 0.0 years remaining

Serial test patterns for mosfet testing

Assignee: International Business Machines Corp
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Filing: 1972-03-27
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Granted: 1974-02-05
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Expires: 1992-03-27
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Abstract

Abstract A technique of decreasing the number of test patterns required to test a MOSFET module and/or provide the ability to test elements on the module which can not be tested by conventional test techniques. Conventionally, test patterns are applied to the input pins of a MOSFET module and the output monitored at the output pins of the module. Interwoven with the normal test pattern testing is the application of a serial test pattern to selected elements on the module. The serial test pattern is applied to a single input pin on the module and a serial test pattern is stored in a shift register which is on the module. Each of the stages of the shift register are used to control or monitor an element or point which may be otherwise inaccessible or untestable and the shift register is also utilized in an output mode to provide an indication serially on a single output pin as to the functioning of the points accessed on the module. The sequence then is to input onto a single input pin a serial test pattern for testing, controlling or monitoring various elements or nets on the module; reload the shift register in accordance with the test results; and then serially shift the contents of the shift register out onto the single output pin while monitoring this output to determine whether the elements or nets are functioning properly. In addition, while the serial test pattern is applied the output appearing at the output pins of the module may be monitored.

Inventors

  • 👤 R James

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 22:24
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 85 words
A method of testing a large scale integrated logical chip device having functional input and output pins in logical communication with logical elements and nets on said logical device, said method comprising: adding on to said logical chip device shift register storage means for holding a test pattern, loading a test pattern into said shift register storage means, applying said test pattern to selected elements on said logical chip device; and monitoring the results of said application of said test pattern to said selected elements.
Claim 2
Independent Claim 85 words
A method of testing a large scale integrated logical chip device having functional input and output pins in logical communication with logical elements and nets on said logical device, said method comprising: adding on to said logical chip device shift register storage means for holding a test pattern, loading a test pattern into said shift register storage means, applying said test pattern to selected elements on said logical chip device; and monitoring the results of said application of said test pattern to said selected elements.
Claim 3
Dependent Claim 24 words
The method of testing a large scale integrated logical chip device of claim 1 wherein said test pattern is serially shifted into said register.
Claim 4
Dependent Claim 37 words
The method of testing a large scale integrated logical chip device of claim 2 wherein said shift register is isolated from said selected logical elements during said serial shifting of said test pattern into said shift register.
Claim 5
Dependent Claim 56 words
The methof of testing a large scale integrated logical chip device of claim 3 wherein following said application of said test pattern to said selected logical elements a binary pattern representative of the reaction of said selected logical elements is loaded into said shift register and said binary pattern serially shifted out of said shift register.
Claim 6
Dependent Claim 34 words
The method of testing a large scale integrated logical chip device of claim 4 wherein during the shifting out of said binary pattern said shift register is logically isolated from said selected logical elements.
Claim 7
Dependent Claim 48 words
The method of testing a large scale integrated logical chip device of claim 5 wherein said test pattern is serially applied to said shift register by application to a single input pin and said binary representation is shifted out of said shift register along a single output pin.
Claim 8
Dependent Claim 37 words
The method of testing a large scale integrated logical chip device of claim 6 wherein said serial test pattern is shifted into a first shift register and said binary representation is loaded into a second shift register.
Claim 9
Dependent Claim 48 words
The method of testing a large scale integrated logical chip device of claim 6 wherein following the application of said test pattern to said selected logical elements logical test patterns are applied to said functional input pins and the resultant output appearing on said functional output pins monitored.
Claim 10
Dependent Claim 44 words
The method of testing a large scale integrated logical chip device of claim 8 wherein said shift register is initialized such that all of the stages thereof initially contain a binary 1 or a binary 0 prior to the loading of said test pattern.

References Cited (Backward Citations)

US3590378A Cited
US3582633A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-02-04 1977-08-06 1978-02-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-02-04 1981-08-06 1982-02-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-02-04 1985-08-06 1986-02-05 $7700.00 Window Closed / Lapsed

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