Patent US3789244A successfully refreshed from Google Patents.
US3789244A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fet analog multiplex switch
Assignee: Spacetac Inc
•
Filing: 1972-09-08
•
Granted: 1974-01-29
•
Expires: 1992-09-08
Abstract
Abstract An FET analog switching circuit, including an input terminal and an output terminal, first and second FET''s connected together with their primary electrodes connected in series between the input terminal and the output terminal, one of the first and second FET''s being an N type and the other being a P type, and means for selectively applying a switching signal of one polarity to the gate of the first FET to turn on the first FET and of the opposite polarity to the gate of the second FET to simultaneously turn on the second FET.
Inventors
- 👤 S Provanzano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:05
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K17/6872
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
199 words
An FET analog switching circuit comprising an input terminal and an output terminal, first and second FET''s connected together with their primary electrodes connected in series between said input terminal and said output terminal one of said first and second FET''s being an N type, and the other being a P type; one of said FET''s being arranged with its source electrode connected to said input terminal and its drain electrode connected to the drain electrode of the other FET, the other FET having its source electrode connected to said output terminal, the one of said FET''s connected to said input terminal also having its body electrode connected to its drain electrode and the FET connected to said output terminal also having its body electrode connected to a source of voltage of the same polarity as and equal to or greater than the amplitude of the voltage presented to the FET connected to said input terminal; and means for selectively applying a switching signal of one polarity to the gate of the first FET to turn on said first FET and of the opposite polarity to the gate of said second FET tO simultaneously turn on said second FET.
Claim 2
Dependent Claim
199 words
An FET analog switching circuit comprising an input terminal and an output terminal, first and second FET''s connected together with their primary electrodes connected in series between said input terminal and said output terminal one of said first and second FET''s being an N type, and the other being a P type; one of said FET''s being arranged with its source electrode connected to said input terminal and its drain electrode connected to the drain electrode of the other FET, the other FET having its source electrode connected to said output terminal, the one of said FET''s connected to said input terminal also having its body electrode connected to its drain electrode and the FET connected to said output terminal also having its body electrode connected to a source of voltage of the same polarity as and equal to or greater than the amplitude of the voltage presented to the FET connected to said input terminal; and means for selectively applying a switching signal of one polarity to the gate of the first FET to turn on said first FET and of the opposite polarity to the gate of said second FET tO simultaneously turn on said second FET.
Claim 3
Dependent Claim
45 words
The circuit of claim 1 in which said means for selectively applying includes an inverter with its output connected to one of said FET''s and its input connected to the other of said FET''s and to a control terminal adapted to receive a switching input.
Claim 4
Dependent Claim
52 words
The circuit of claim 1 further including a reverse biasing circuit for maintaining a substantial reverse bias of one polarity on one of said first and second FET''s and of the opposite polarity on the other of said FET''s in their off states to prevent accidental switching of each of said FET''s.
Claim 5
Dependent Claim
34 words
The circuit of claim 1 in which the N type one of said FET''s has its source connected to said input terminal and the P type has its source connected to said output terminal.
Claim 6
Dependent Claim
34 words
The circuit of claim 1 in which said P type one of said FET''s has its source connected to said input terminal and said N type has its source connected to said output terminal.
Claim 7
Dependent Claim
155 words
An FET analog switching circuit comprising an input terminal and an output terminal, first and second FET''s connected together with their primary electrodes connected in series between said input terminal and said output terminal, one of said first and second FET''s being an N type, and the other being a P type; said N type one of said FET''s having its body electrode connected to its drain electrode and said P type one of said FET''s having its body electrode connected to a positive voltage level approximately equal to or greater than the voltage level of the switching signal applied to the gate electrode of the N type one of said FET''s, and means for selectively applying a switching signal of one polarity to the gate of the first FET to turn on said first FET and of the opposite polarity to the gate of said second FET to simultaneously turn on said second FET.
Claim 8
Dependent Claim
155 words
An FET analog switching circuit comprising an input terminal and an output terminal, first and second FET''s connected together with their primary electrodes connected in series between said input terminal and said output terminal, one of said first and second FET''s being an N type, and the other being a P type; said N type one of said FET''s having its body electrode connected to its drain electrode and said P type one of said FET''s having its body electrode connected to a positive voltage level approximately equal to or greater than the voltage level of the switching signal applied to the gate electrode of the N type one of said FET''s, and means for selectively applying a switching signal of one polarity to the gate of the first FET to turn on said first FET and of the opposite polarity to the gate of said second FET to simultaneously turn on said second FET.
Claim 9
Dependent Claim
155 words
An FET analog switching circuit comprising an input terminal and an output terminal, first and second FET''s connected together with their primary electrodes connected in series between said input terminal and said output terminal, one of said first and second FET''s being an N type, and the other being a P type; said P type one of said FET''s having its body electrode connected to its drain electrode and said N type one of said FET''s having its body electrode connected to a negative voltage level approximately equal to or greater than the voltage level of the switching signal applied to the gate electrode of the P type one of said FET''s and means for selectively applying a switching signal of one polarity to the gate of the first FET to turn on said first FET and of the opposite polarity to the gate of said second FET to simultaneously turn on said second FET.
Claim 10
Dependent Claim
155 words
An FET analog switching circuit comprising an input terminal and an output terminal, first and second FET''s connected together with their primary electrodes connected in series between said input terminal and said output terminal, one of said first and second FET''s being an N type, and the other being a P type; said P type one of said FET''s having its body electrode connected to its drain electrode and said N type one of said FET''s having its body electrode connected to a negative voltage level approximately equal to or greater than the voltage level of the switching signal applied to the gate electrode of the P type one of said FET''s and means for selectively applying a switching signal of one polarity to the gate of the first FET to turn on said first FET and of the opposite polarity to the gate of said second FET to simultaneously turn on said second FET.
References Cited (Backward Citations)
US3089963A
Cited
US3183366A
Cited
US3023321A
Cited
US3189758A
Cited
US3488520A
Cited
US3533087A
Cited
US3521141A
Cited
US3584236A
Cited
US3466526A
Cited
US3569737A
Cited
US3631528A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-28 | 1977-07-30 | 1978-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-28 | 1981-07-30 | 1982-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-28 | 1985-07-30 | 1986-01-29 | $7700.00 | Window Closed / Lapsed |