Fail-safe transistor gate circuit

Claim 2

A fail-safe logic circuit comprising a solid-state electronic gate, said solid-state electronic gate including a first and a second transistor each having an emitter, a collector and a base electrode, a gated source of AC input signals selectively connected to said emitter electrode of said first transistor, a first gated source of DC potential selectively connected to said base electrode of said first transistor, a first ground connection coupled to said emitter and base electrodEs of said first transistor, said collector electrode of said first transistor coupled to the emitter of said second transistor, a second gated source of DC potential selectively coupled to said base electrode of said second transistor, and second ground connection coupled to said emitter and base electrodes of said second transistor wherein AC output signals are present on the collector electrode of said second transistor when and only when said source of AC input signals and said sources of DC biasing potentials are gated on, said ground connection is intact and a critical circuit failure is absent.

Claim 3

A fail-safe logic circuit as defined in claim 1 wherein, said first transistor is of an NPN type.

Claim 4

A fail-safe logic circuit as defined in claim 1, wherein a voltage divider network including a first and a second resistor connects said source of DC potential to said base electrode of said first transistor.

Claim 5

A fail-safe logic circuit as defined in claim 3, wherein a bypass capacitor is connected across said first resistor.

Claim 6

A fail-safe logic circuit as defined in claim 1, wherein a current-limiting resistor connects said source of AC input signals to said emitter electrode of said first transistor.

Claim 7

A fail-safe logic circuit as defined in claim 1, wherein a biasing resistor is coupled between said emitter electrode of said transistor and said first ground connection.

Claim 8

A fail-safe logic circuit comprising a pair of cascaded complementary transistor amplifiers, each of said transistor amplifiers having an input, an output and a common electrode, a source of AC input signals coupled to the input electrode of one of said complementary transistor amplifiers, a first source of DC biasing potential coupled to said common electrode of said one complementary transistor, a first ground connection coupled to said input and common electrodes of said one complementary transistor, said output electrode of said one complementary transistor coupled to the input electrode of the other of said complementary transistors, a second source of DC biasing potential coupled to said common and said input electrodes of said other complementary transistor, a second ground connection coupled to said common electrode of said other complementary transistor, a load device coupled to said output electrode of said other complementary transistor and being energized when and only when said AC input signals and said first and said second DC biasing potentials are present, said first and second ground connections are intact and barring a critical circuit failure.

Claim 9

A fail-safe logic circuit comprising a pair of cascaded complementary transistor amplifiers, each of said transistor amplifiers having an input, an output and a common electrode, a source of AC input signals coupled to the input electrode of one of said complementary transistor amplifiers, a first source of DC biasing potential coupled to said common electrode of said one complementary transistor, a first ground connection coupled to said input and common electrodes of said one complementary transistor, said output electrode of said one complementary transistor coupled to the input electrode of the other of said complementary transistors, a second source of DC biasing potential coupled to said common and said input electrodes of said other complementary transistor, a second ground connection coupled to said common electrode of said other complementary transistor, a load device coupled to said output electrode of said other complementary transistor and being energized when and only when said AC input signals and said first and said second DC biasing potentials are present, said first and second ground connections are intact and barring a critical circuit failure.

Claim 10

A fail-safe logic circuit as defined in claim 7, wherein each of said transistor amplifiers are connected in a common-base configuration.

Claim 11

An electronic gating circuit comprising in combination, first and second transistors of the opposite conductivity type with each having an emitter, a collector and a base electrode, a first voltage divider network including a first and a second resistor and a capacitor bypassing said first resistor for providing a substantially constant biasing potential on said base electrode of said first transistor, a first current-limiting resistor for applying AC input signals to said emitter electrode of said first transistor, a first biasing resistor for connecting said emitter electrode of said first transistor to a reference potential, a second voltage divider network including a first and a second resistor and a capacitor bypassing said first resistor for providing a substantially constant biasing potential on said base electrode of said second transistor, a second biasing resistor for providing emitter biasing potential on said emitter electrode of said second transistor, a second current-limiting resistor coupling said collector electrode of said first transistor to the emitter electrode of said second transistor, and means for deriving AC output signals from said collector electrode of said second transistor when the biasing potentials are at a predeterminEd level and the AC input signals are present and a critical circuit failure is absent.

Claim 12

An electronic gating circuit comprising in combination, first and second transistors of the opposite conductivity type with each having an emitter, a collector and a base electrode, a first voltage divider network including a first and a second resistor and a capacitor bypassing said first resistor for providing a substantially constant biasing potential on said base electrode of said first transistor, a first current-limiting resistor for applying AC input signals to said emitter electrode of said first transistor, a first biasing resistor for connecting said emitter electrode of said first transistor to a reference potential, a second voltage divider network including a first and a second resistor and a capacitor bypassing said first resistor for providing a substantially constant biasing potential on said base electrode of said second transistor, a second biasing resistor for providing emitter biasing potential on said emitter electrode of said second transistor, a second current-limiting resistor coupling said collector electrode of said first transistor to the emitter electrode of said second transistor, and means for deriving AC output signals from said collector electrode of said second transistor when the biasing potentials are at a predeterminEd level and the AC input signals are present and a critical circuit failure is absent.