Integrated circuit structure having electrically isolated circuit components

Claim 2

A semiconductor device structure comprising: an insulating substrate, a semiconductor body including a plurality of semiconductor regions disposed upon said insulating substrate, an insulating layer at least partially covering the surface of said semiconductor body opposite from said insulating substrate, selectively etched-out regions formed in said semiconductor body and extending through the thickness of said semiconductor body and said insulating layer to define at least one channel extending between and separating at least two of said semiconductor regions to provide electrical isolation therebetween, a circuit component within at least one of said semiconductor regions, said insulating layer being provided with an opening therethrough in registration with a portion of said circuit component, and a metallic layer of substantially uniform thickness defining an elongated electrically conductive lead connected to said circuit component through the opening in said insulating layer, said metallic layer being arranged in juxtaposed engaging relation to said insulating layer except for a portion thereof extending across and bridging said at least one channel.

Claim 3

A semiconductor device structure as set forth in claim 1, further including a circuit component within at least the other of said two separated electrically isolated semiconductor regions, and said metallic layer extending into connecting engagement with the circuit component within said other semiconductor region so as to provide an ohmic interconnection between said circuit components of said two separated electrically isolated semiconductor regions, whereby said semiconductor device structure comprises an integrated circuit.

Claim 4

A semiconductor device structure as set forth in claim 1, wherein said insulating substrate comprises a composite substrate including a support layer of semiconductor material, and an insulating layer covering said support layer of said semiconductor material and on which said semicondcutor body is disposed.

Claim 5

A semiconductor device structure as set forth in claim 3, wherein said support layer is made of polycrystalline semiconductor material.

Claim 6

A semiconductor device structure comprising: an insulating substrate, a semiconductor body including a plurality of semiconductor regions disposed upon said insulating substrate, an insulating layer at least partially covering the surface of said semiconductor body opposite from said insulating substrate, selectively etched-out regions formed in said semiconductor body and extending through the thickness of said semiconductor body and said insulating layer to define at least one channel extending between and separating at least two of said semiconductor regions to provide electrical isolation therebetween, a circuit component within at least one of said semiconductor regions, said insulating layer being provided with an opening therethrough in registration with a portion of said circuit component, and a metallic layer of substantially uniform thickness defining an elongated electrically conductive lead connected to said circuit component through the opening in said insulating layer, said metallic layer including a portion extending across and bridging said at least one channel and disposed transversely with respect to the longitudinal extent of said channel such that a major portion of the mouth of said channel is open on the surface of said insulating layer remote from said semiconductor body, and the remainder of said metallic layer bieng arranged in juxtaposed engaging relation to said insulating layer on both sides of said channel.

Claim 7

A semiconductor device structure comprising: an insulating substrate, a semiconductor body including a plurality of semiconductor regions disposed upon said insulating substrate, an insulating layer at least partially covering the surface of said semiconductor body opposite from said insulating substrate, selectively etched-out regions formed in said semiconductor body and extending through the thickness of said semiconductor body and said insulating layer to define at least one channel extending between and separating at least two of said semiconductor regions to provide electrical isolation therebetween, a circuit component within at least one of said semiconductor regions, said insulating layer being provided with an opening therethrough in registration with a portion of said circuit component, and a metallic layer of substantially uniform thickness defining an elongated electrically conductive lead connected to said circuit component through the opening in said insulating layer, said metallic layer including a portion extending across and bridging said at least one channel and disposed transversely with respect to the longitudinal extent of said channel such that a major portion of the mouth of said channel is open on the surface of said insulating layer remote from said semiconductor body, and the remainder of said metallic layer bieng arranged in juxtaposed engaging relation to said insulating layer on both sides of said channel.

Claim 8

A semiconductor device structure as set forth in claim 5, wherein said selectively etched-out regions define a plurality of channels which are are so positioned as to separate respective ones of said semiconductor regions from other semiconductor regions included in said plurality of semiconductor regions to provide electrical isolation between each pair of semiconductor regions so separated, at least some of said semiconductor regions having a circuit component therewithin, said metallic laYer being a patterned metallic layer at least providing a plurality of individual elongated electrically conductive leads selectively providing ohmic interconnections between circuit components of respective semiconductor regions in a predetermined manner to comprise an integrated circuit, each of said plurality of elongated conductive leads including a portion extending across and bridging a respective one of said channels and disposed transversely with respect to the longitudinal extent thereof, the remainder of said conductive lead being disposed in juxtaposed engaging relation to said insulating layer on both sides of the said one channel, and a major portion of the mouth of each of said plurality of channels being open on the surface of said insulating layer remote from said semiconductor body.

Claim 9

A semiconductor device structure comprising: an insulating substrate, a semiconductor body including a plurality of semiconductor regions disposed upon said insulating substrate, an insulating layer at least partially covering the surface of said semiconductor body opposite from said insulating substrate, selectively etched-out regions formed in said semiconductor body and extending through the thickness of said semiconductor body and said insulating layer to define at least one channel extending between and separating at least two of said semiconductor regions to provide electrical isolation therebetween, a circuit component within at least one of said semiconductor regions, said insulating layer being provided with an opening therethrough in registration with a portion of said circuit component, a metallic layer of substantially uniform thickness disposed on said insulating layer and defining an elongated electrically conductive lead connected to said circuit component through the opening in said insulating layer, said metallic layer being arranged in juxtaposed engaging relation to said insulating layer except for a portion thereof extending across and bridging said at least one channel, and said metallic layer terminating at one end thereof in an enlarged bonding pad comprising an expanded contact on the side of said channel remote from the semiconductor region in which said circuit component is disposed.

Claim 10

A semiconductor device structure comprising: an insulating substrate, a semiconductor body including a plurality of semiconductor regions disposed upon said insulating substrate, an insulating layer at least partially covering the surface of said semiconductor body opposite from said insulating substrate, selectively etched-out regions formed in said semiconductor body and extending through the thickness of said semiconductor body and said insulating layer to define at least one channel extending between and separating at least two of said semiconductor regions to provide electrical isolation therebetween, a circuit component within at least one of said semiconductor regions, said insulating layer being provided with an opening therethrough in registration with a portion of said circuit component, a metallic layer of substantially uniform thickness disposed on said insulating layer and defining an elongated electrically conductive lead connected to said circuit component through the opening in said insulating layer, said metallic layer being arranged in juxtaposed engaging relation to said insulating layer except for a portion thereof extending across and bridging said at least one channel, and said metallic layer terminating at one end thereof in an enlarged bonding pad comprising an expanded contact on the side of said channel remote from the semiconductor region in which said circuit component is disposed.

Claim 11

A semiconductor device structure comprising: an insulating substrate, a semiconductor body including a plurality of semiconductor regions disposed upon said insulating substrate, said plurality of semiconductor regions including a first region of one conductivity type material disposed adjacent to said insulating substrate, a second region of opposite conductivity material disposed within said first region, and a third region of said one conductivity type material disposed within said second region, each of said first, second, and third semiconductor regions extending to the surface of said semiconductor body remote from said insulating substrate and defining portions of said surface of said semiconductor body, an insulating layer at least partially covering said surface of said semiconductor body remote from said insulating substrate including portions of said first, second, and third semiconductor regions, selectively etched-out regions formed in said semiconductor body and extending through the thickness of said semiconductor body and said insulating layer to define an endless channel within which said first, second, and third semiconductor regions are enclosed to separate said first, second, and third semiconductor regions from the remainder of said semiconductor body to provide electrical isolation therefor, said insulating layer being provided with respective openings therethrough in registration with portions of said first, second, and third semiconductor regions, a patterned metallic layer of substantially uniform thickness disposed on said insulating layer and defining a plurality of elongated electrically conductive leads connected to corresponding ones of said first, second, and third semiconductor regions through the respective openings in said insulating layer, said electrically conductive leads being arranged in juxtaposed engaging relation to said insulating layer except for respective portions thereof extending across and bridging said endless channel within which said first, second, and third semiconductor regions are disposed, and each of said electrically conductive leads including an enlarged bonding pad comprising an expanded contact at the end thereof disposed on said insulating layer outwardly with respect to said endless channel and remote from the connection of said lead to the corresponding one of said first, second, and third semiconductor regions.

Claim 12

A semiconductor device structure comprising: an insulating substrate, a semiconductor body including a plurality of semiconductor regions disposed upon said insulating substrate, said plurality of semiconductor regions including a first region of one conductivity type material disposed adjacent to said insulating substrate, a second region of opposite conductivity material disposed within said first region, and a third region of said one conductivity type material disposed within said second region, each of said first, second, and third semiconductor regions extending to the surface of said semiconductor body remote from said insulating substrate and defining portions of said surface of said semiconductor body, an insulating layer at least partially covering said surface of said semiconductor body remote from said insulating substrate including portions of said first, second, and third semiconductor regions, selectively etched-out regions formed in said semiconductor body and extending through the thickness of said semiconductor body and said insulating layer to define an endless channel within which said first, second, and third semiconductor regions are enclosed to separate said first, second, and third semiconductor regions from the remainder of said semiconductor body to provide electrical isolation therefor, said insulating layer being provided with respective openings therethrough in registration with portions of said first, second, and third semiconductor regions, a patterned metallic layer of substantially uniform thickness disposed on said insulating layer and defining a plurality of elongated electrically conductive leads connected to corresponding ones of said first, second, and third semiconductor regions through the respective openings in said insulating layer, said electrically conductive leads being arranged in juxtaposed engaging relation to said insulating layer except for respective portions thereof extending across and bridging said endless channel within which said first, second, and third semiconductor regions are disposed, and each of said electrically conductive leads including an enlarged bonding pad comprising an expanded contact at the end thereof disposed on said insulating layer outwardly with respect to said endless channel and remote from the connection of said lead to the corresponding one of said first, second, and third semiconductor regions.