Reversible 2{40 s complement to sign-magnitude converter

Claim 2

In combination, means for providing a two''s complement to sign magnitude control signal, means for carrying out an EXCLUSIVE OR logic operation between input numerical digits of a signed binary coded signal representation and an inverted sign digit signal of said input representation, means for producing an inversion control signal in response to either a. a first predetermined signal state of said sign digit signal, or b. a simultaneous occurrence of a second state of said sign digit signal, a first state of all of said numerical digit signals, and a second state of said two''s complement to sign magnitude control signal, means for inverting outputs of said EXCLUSIVE OR means in response to said inversion control signal, whereby the first produced inversion control signal reversibly controls Conversions between positive sign magnitude and positive two''s complement signal representations whereas the second produced inversion control signal controls conversion of a negative overflow character in two''s complement signal representation to a negative overflow character in sign magnitude signal representation, and means for coupling said sign digit signal to an output with said inverting means output and including means, responsive to said first state of all of said numerical digits and a first state of said two''s complement to sign magnitude control signal, for forcing said sign digit signal to said first state thereof whereby a negative zero character in sign magnitude signal representation is converted to a zero character in two''s complement signal representation.

Claim 3

In combination means for providing a two''s complement to sign magnitude binary control signal, means for carrying out an EXCLUSIVE OR logic operation between input numerical digits of a signed binary coded signal representation and an inverted sign digit signal of said input representation, means for producing an inversion control signal in response to either a. a first predetermined signal state of said sign digit signal, or b. a simultaneous occurrence of a second state of said sign digit signal and a first state of all of said numerical digit signals, means for inverting outputs of said EXCLUSIVE OR means in response to said inversion control signal, means for coupling said sign digit signal to an output with said inverting means output and including means, responsive to said first state of all of said numerical digits, for forcing said sign digit signal to said first state, and means responsive to a first state of said two''s complement to sign magnitude control signal for disabling operation of said producing means in response to said simultaneous occurrence whereby said signed binary coded signal is converted from a sign magnitude to a two''s complement signal representation, and said means being further responsive to a second state of said two''s complement to sign magnitude control signal for disabling said forcing means and enabling said producing means whereby said signed binary coded signal is converted from a two''s complement to a sign magnitude signal representation.

Claim 4

In combination means for providing a two''s complement to sign magnitude binary control signal, means for carrying out an EXCLUSIVE OR logic operation between input numerical digits of a signed binary coded signal representation and an inverted sign digit signal of said input representation, means for producing an inversion control signal in response to either a. a first predetermined signal state of said sign digit signal, or b. a simultaneous occurrence of a second state of said sign digit signal and a first state of all of said numerical digit signals, means for inverting outputs of said EXCLUSIVE OR means in response to said inversion control signal, means for coupling said sign digit signal to an output with said inverting means output and including means, responsive to said first state of all of said numerical digits, for forcing said sign digit signal to said first state, and means responsive to a first state of said two''s complement to sign magnitude control signal for disabling operation of said producing means in response to said simultaneous occurrence whereby said signed binary coded signal is converted from a sign magnitude to a two''s complement signal representation, and said means being further responsive to a second state of said two''s complement to sign magnitude control signal for disabling said forcing means and enabling said producing means whereby said signed binary coded signal is converted from a two''s complement to a sign magnitude signal representation.

Claim 5

In combination, a first pluarlity of EXCLUSIVE OR gates, one for each numerical digit of a signed, ordered, binary signal representation, means for applying each of said numerical digits to a first input of a different one of said gates, means for applying a sign digit signal of said representation, in inverted form, to a second output of the lowest ordered one of said gates, means for coupling to a second input of each of said gates, except said one gate, either said sign digit signal or the signals from any lower ordered gate first input, a second plurality of EXCLUSIVE OR gates, equal in number to said first plurality and each having an input connected to receive an output of a different one of said first plurality of gates, and means, responsive to a predetermined function of said sign digit signal, a two''s complement to sign magnitude control signal, and said numerical digit signals, for controlling said second plurality of gates for selectably inverting outputs of said first plurality of gates in accordance with said function whereby said signed, ordered, binary signal representation is reversibly converted between sign magnitude and two''s complement signal representations.

Claim 6

In combination, a first pluarlity of EXCLUSIVE OR gates, one for each numerical digit of a signed, ordered, binary signal representation, means for applying each of said numerical digits to a first input of a different one of said gates, means for applying a sign digit signal of said representation, in inverted form, to a second output of the lowest ordered one of said gates, means for coupling to a second input of each of said gates, except said one gate, either said sign digit signal or the signals from any lower ordered gate first input, a second plurality of EXCLUSIVE OR gates, equal in number to said first plurality and each having an input connected to receive an output of a different one of said first plurality of gates, and means, responsive to a predetermined function of said sign digit signal, a two''s complement to sign magnitude control signal, and said numerical digit signals, for controlling said second plurality of gates for selectably inverting outputs of said first plurality of gates in accordance with said function whereby said signed, ordered, binary signal representation is reversibly converted between sign magnitude and two''s complement signal representations.

Claim 7

In combination, means for providing a two''s complement to sign magnitude control signal, first and second stages of ordered multibit EXCLUSIVE OR logic for transmitting numerical digit signals of binary coded signal representations that also include a sign digit position signal, means for coupling said stages in tandem, means for controlling said first stage to invert all of said numerical digit signals if said sIgn signal is in a first signal state or, if said sign signal is in a second signal state, to invert any of said numerical digit signals in numerical digit positions of higher order than one of such numerical signals in a second signal state, means for controlling said second stage to invert all of said numerical digit signals from said first stage if said sign digit is in said first state, whereby reverisble conversions are effected between positive two''s complement and sign magnitude signal representations, or if all of said numerical signal digits are in said first state when said sign digit is in said second state and said two''s complement to sign magnitude control signal is in a second state, whereby a negative overflow character in two''s complement signal representation is converted to a negative overflow character in sign magnitude signal representation, and means for inverting said sign digit signal when all of said numerical signal digits are in said first state, said sign digit is in said second state, and said two''s complement to sign magnitude control signal is in a first state whereby a negative zero character in sign magnitude signal representation is converted to a zero character in two''s complement signal representation.

Claim 8

In combination, means for providing a two''s complement to sign magnitude control signal, first and second stages of ordered multibit EXCLUSIVE OR logic for transmitting numerical digit signals of binary coded signal representations that also include a sign digit position signal, means for coupling said stages in tandem, means for controlling said first stage to invert all of said numerical digit signals if said sIgn signal is in a first signal state or, if said sign signal is in a second signal state, to invert any of said numerical digit signals in numerical digit positions of higher order than one of such numerical signals in a second signal state, means for controlling said second stage to invert all of said numerical digit signals from said first stage if said sign digit is in said first state, whereby reverisble conversions are effected between positive two''s complement and sign magnitude signal representations, or if all of said numerical signal digits are in said first state when said sign digit is in said second state and said two''s complement to sign magnitude control signal is in a second state, whereby a negative overflow character in two''s complement signal representation is converted to a negative overflow character in sign magnitude signal representation, and means for inverting said sign digit signal when all of said numerical signal digits are in said first state, said sign digit is in said second state, and said two''s complement to sign magnitude control signal is in a first state whereby a negative zero character in sign magnitude signal representation is converted to a zero character in two''s complement signal representation.

Claim 9

In combination, means for providing a two''s complement to sign magnitude control signal, means, responsive to multiple ordered binary signal bits including numerical bits and a sign bit, for detecting coincidence of a second signal state in said sign bit and a first signal state in all of said numerical bits with said coincidence condition representing either negative zero in sign magnitude representation or negative overflow in two''s complement representation, respectively, said detecting means providing an enabling signal in response to said coincidence, means for receiving said two''s complement to sign magnitude control signal, and means, responsive to said enabling signal and a first state of said two''s complement to sign magnitude control signal, for forcing said sign bit to a first state and leaving said numerical bits in said first state whereby negative zero in sign magnitude representation is converted to its equivalent two''s complement representation, with said forcing means in response to a second signal state of said two''s complement to sign magnitude control signal forcing said numerical bits to said second state and leaving said sign bit in said second state whereby negative overflow in two''s complement representation is converted to the most negative quantity in sign magnitude representation.

Claim 10

In combination, means for providing a two''s complement to sign magnitude control signal, means, responsive to multiple ordered binary signal bits including numerical bits and a sign bit, for detecting coincidence of a second signal state in said sign bit and a first signal state in all of said numerical bits with said coincidence condition representing either negative zero in sign magnitude representation or negative overflow in two''s complement representation, respectively, said detecting means providing an enabling signal in response to said coincidence, means for receiving said two''s complement to sign magnitude control signal, and means, responsive to said enabling signal and a first state of said two''s complement to sign magnitude control signal, for forcing said sign bit to a first state and leaving said numerical bits in said first state whereby negative zero in sign magnitude representation is converted to its equivalent two''s complement representation, with said forcing means in response to a second signal state of said two''s complement to sign magnitude control signal forcing said numerical bits to said second state and leaving said sign bit in said second state whereby negative overflow in two''s complement representation is converted to the most negative quantity in sign magnitude representation.

Claim 11

In combination, means for providing a two''s complement to sign magnitude control signal, means for carrying out a series of OR logic operations between input numerical digit or an ordered binary coded signal and a succession of OR logic input signals to produce an enabling signal, with the first input signal in said succession being an inverted sign digit signal of said ordered binary coded signal and each succeeding stage in said series deriving one of its inputs from a directly preceding stage, with said numerical digit signals being applied to said series in progressive order from a least significant digit to a more significant digit, means for carrying out an EXCLUSIVE OR logic operation between each of said numerical digits of said ordered binary coded signal and each of said OR logic input signals, means for producing an inversion control signal in response to said enabling signal, said inverted sign digit signal, and said two''s complement to sign magnitude control signal, means for inverting outputs of said EXCLUSIVE OR means in response to said inversion control signal, whereby reversible conversions are effected between sign magnitude and two''s complement signal representations, and means, responsive to said enabling signal and to said two''s complement to sign magnitude control signal, for forcing said sign digiT signal to a predetermined state.

Claim 12

In combination, means for providing a two''s complement to sign magnitude control signal, means for carrying out a series of OR logic operations between input numerical digit or an ordered binary coded signal and a succession of OR logic input signals to produce an enabling signal, with the first input signal in said succession being an inverted sign digit signal of said ordered binary coded signal and each succeeding stage in said series deriving one of its inputs from a directly preceding stage, with said numerical digit signals being applied to said series in progressive order from a least significant digit to a more significant digit, means for carrying out an EXCLUSIVE OR logic operation between each of said numerical digits of said ordered binary coded signal and each of said OR logic input signals, means for producing an inversion control signal in response to said enabling signal, said inverted sign digit signal, and said two''s complement to sign magnitude control signal, means for inverting outputs of said EXCLUSIVE OR means in response to said inversion control signal, whereby reversible conversions are effected between sign magnitude and two''s complement signal representations, and means, responsive to said enabling signal and to said two''s complement to sign magnitude control signal, for forcing said sign digiT signal to a predetermined state.

Claim 13

The combination in accordance with claim 6 in which the means for producing the inversion control signal includes means responsive to said inverted sign digit signal for enabling said producing means when said sign digit signal is in a first signal state.

Claim 14

The combination in accordance with claim 6 in which the means for producing the inversion control signal includes means for inverting said signal resulting from said series of OR logic operations when all of said numerical digits of said ordered binary coded signal are in a first signal state and said sign digit signal is in a second signal state, means, responsive to said inverted signal and to a second signal state of said two''s complement-sign magnitude control signal, for generating an enabling signal for said producing means.