Binary register

Claim 2

Binary register circuit apparatus for storing multiorder binary numbers, said circuit apparatus comprising in combination: a plurality of bistable means for storing said binary numbers, each of said bistable means being associated with a mutually exclusive one of the orders of said binary numbers, each of said bistable means having input means and output means, respectively; and selectable control means for selectively applying a first signal to the respective input means of said plurality of bistable means to provide at the respective output means of said plurality of bistable means the one''s complement of the binary number stored therein and a second signal to the respective input means of the ones of said plurality of bistable means associated with the next-to-lowest order and the succeeding orders thereof to provide at the respective output means of said plurality of bistable means the two''s complement of the binary number stoRed therein.

Claim 3

Binary register circuit apparatus according to claim 1 wherein said selectable means further alternately applies said first and second signals in pairs, said circuit apparatus in response to each pair of alternate signals being advanced from a binary number in a given series to the next binary number of the series.

Claim 4

Binary register circuit apparatus according to claim 2 wherein the binary numbers of said given series are consecutive and correspond to consecutive decimal numbers, said circuit apparatus being advanced in the forward direction when each signal pair is applied in the sequence of a said first signal and a subsequent said second signal, and said circuit apparatus being advanced in the reverse direction when each signal pair is applied to an opposite sequence of a said second signal and a subsequent first signal.

Claim 5

Binary register circuit apparatus according to claim 1 wherein said selectable means further comprises: a plurality of logic stages for intercoupling said bistable means, each of said logic stages being associated with a particular one of the higher order bistable means and coupling the input means of the particular higher order bistable means associated therewith to the respective outputs of the preceding lower order bistable means, said higher order bistable means being the ones of said plurality of bistable means associated with the next-to-lowest and succeeding orders of the binary numbers.

Claim 6

Binary register circuit apparatus according to claim 4 wherein each of said logic stages comprises at least: first two input OR gate means having an output coupled to the input means of the particular higher order bistable means associated therewith, and two input AND gate means having an output coupled to one of the inputs of the first OR gate means of the particular logic stage thereof, the other inputs of each of said first OR gate means being commonly coupled to each other and to the input means of the lowest order bistable means; and wherein each of said logic stages associated with the next-to-next lowest order stage and the succeeding order stages thereto further comprises: second two input OR gate means having an output coupled to one of the inputs of the AND gate means of the particular logic stage thereof and to one of the inputs of the second OR gate means of the logic stage associated with the succeeding order bistable means, the other input of the second OR gate means being coupled to the output means of the preceding lower order bistable means, the other input of the second OR gate means of the logic stage associated with the next-to-next lowest order bistable means being coupled to the output means of the lowest order bistable means; and the output means of the lowest order bistable means being coupled further to one of the inputs of the AND gate means of the logic stage associated with the next-to-lowest bistable means, and the other inputs of the AND gate means of each of the logic stages being commonly coupled to each other.

Claim 7

Binary register circuit apparatus according to claim 1 further comprising detector means for detecting the simultaneous presence of binary 0 levels at each of said output means.

Claim 8

Binary register circuit apparatus according to claim 1 wherein said detector means comprises an OR type logic circuit means for ORing said output means.

Claim 9

Bistable register circuit apparatus according to claim 1 wherein each of said bistable means further comprises: a multivibrator having a complementary input, said input means of a particular bistable means comprising the particular complementary input of the multivibrator thereof.

Claim 10

A binary register for storing multiorder binary coded digital information, said register comprising in combination: a plurality of bistable means, each of said bistable means being associated with a mutually exclusive one of the orders of said binary coded information and having input meanS and output means, respectively; and control means coupling the output means of each bistable means to the respective input means of each of the succeeding higher order bistable means, said control means having first control input means and second control input means, respectively, said first control input means being commonly coupled to the input means of said plurality of bistable means, and said second control input means being commonly coupled to the input means of the next-to-last lowest order and each succeeding higher order ones of said plurality of output means; said register being set to the one''s complement of its previous state in response to a first signal applied to said first control input means and being set to the two''s complement of its previous state in response to a second signal applied to said second control input means.

Claim 11

A binary register for storing multiorder binary coded digital information, said register comprising in combination: a plurality of bistable means, each of said bistable means being associated with a mutually exclusive one of the orders of said binary coded information and having input meanS and output means, respectively; and control means coupling the output means of each bistable means to the respective input means of each of the succeeding higher order bistable means, said control means having first control input means and second control input means, respectively, said first control input means being commonly coupled to the input means of said plurality of bistable means, and said second control input means being commonly coupled to the input means of the next-to-last lowest order and each succeeding higher order ones of said plurality of output means; said register being set to the one''s complement of its previous state in response to a first signal applied to said first control input means and being set to the two''s complement of its previous state in response to a second signal applied to said second control input means.

Claim 12

A binary register according to claim 9 wherein said first and second signals are applied alternately to the first and second control input means, respectively, in a predetermined sequence to cause said register to count in a first direction.

Claim 13

A binary register according to claim 9 wherein said first and second signals are applied to the first and second control input means, respectively, to cause said register to count, said register counting in the forward direction whenever the control signals are applied in the sequence of a said first signal and a subsequent said second signal, and said register counting in the reverse direction whenever the control signals are applied in the sequence of a said second signal and a subsequent said first signal.

Claim 14

A plural stage binary register for storing binary coded digital information, each of the stages of said register being associated with a mutually exclusive one of the successive binary orders of the binary numbers to be stored therein, said binary register comprising in combination: a plurality of bistable multivibrators having an output and a complementary input, each of said bistable multivibrators being comprised in a mutually exclusive one of the stages of said binary register; each of the stages associated with the next-to-lowest and succeeding orders thereto comprising at least: a first two input OR gate circuit having an output coupled to the complementary input of the multivibrator of the particular stage, and a two input AND gate circuit having an output coupled to one of the inputs of the first OR gate circuit of the particular stage, the other inputs of each of said first OR gate circuits being commonly coupled to each other and to the complementary input of the multivibrator of the lowest order stage to provide a first common input means; and wherein each of the stages associated with the next-to-next lowest order and the succeeding orders thereto further comprises: a second two input OR gate circuit having an output coupled to one of the inputs of the AND gate circuit of the particular stage and to one of the inputs of the second OR gate circuit of the stage associated with the succeeding order, the other input of the second OR gate circuit being coupled to the output of the multivibrator of the preceding lower order stage, the other input of the second OR gate circuit of the stage associated with the next-to-next lowest order being coupled to the output of the multivibrator of the lowest order stage; and the output of the multivibrator of the lowest order stage being coupled further to one of the inputs of the AND gate circuit of the stage associated with the next-to-lowest order, and the other inputs of the AND gate circuit of each of the stages being commonly coupled to each other to provide a second common input.

Claim 15

A plural stage binary register for storing binary coded digital information, each of the stages of said register being associated with a mutually exclusive one of the successive binary orders of the binary numbers to be stored therein, said binary register comprising in combination: a plurality of bistable multivibrators having an output and a complementary input, each of said bistable multivibrators being comprised in a mutually exclusive one of the stages of said binary register; each of the stages associated with the next-to-lowest and succeeding orders thereto comprising at least: a first two input OR gate circuit having an output coupled to the complementary input of the multivibrator of the particular stage, and a two input AND gate circuit having an output coupled to one of the inputs of the first OR gate circuit of the particular stage, the other inputs of each of said first OR gate circuits being commonly coupled to each other and to the complementary input of the multivibrator of the lowest order stage to provide a first common input means; and wherein each of the stages associated with the next-to-next lowest order and the succeeding orders thereto further comprises: a second two input OR gate circuit having an output coupled to one of the inputs of the AND gate circuit of the particular stage and to one of the inputs of the second OR gate circuit of the stage associated with the succeeding order, the other input of the second OR gate circuit being coupled to the output of the multivibrator of the preceding lower order stage, the other input of the second OR gate circuit of the stage associated with the next-to-next lowest order being coupled to the output of the multivibrator of the lowest order stage; and the output of the multivibrator of the lowest order stage being coupled further to one of the inputs of the AND gate circuit of the stage associated with the next-to-lowest order, and the other inputs of the AND gate circuit of each of the stages being commonly coupled to each other to provide a second common input.

Claim 16

A plural stage binary register according to claim 12 further comprising: a two input third OR circuit having an output, one of said inputs of said third OR circuit being connected to the output of the multivibrator of the highest order stage and the other input of sAid third OR circuit being connected to the output of the second OR circuit of the highest order stage.

Claim 17

A plural stage binary register according to claim 12 wherein said register selectively provides a one''s complement of the number stored therefor in response to a first signal applied to said first common input means, and a two''s complement of the number stored therein in response to a second signal applied to said second common input means.

Claim 18

A plural stage binary register according to claim 14 wherein said register further counts in a given direction in response to said first and second signals being alternately applied to said first and second common input means, respectively, in a predetermined sequence.

Claim 19

A plural stage binary register according to claim 15 wherein said register further counts in the opposite direction in response to said first and second signals being alternately applied to said first and second common input means, respectively, in a sequence opposite to said predetermined sequence.