Patent FR714587A successfully refreshed from Google Patents.
Patent US3786282A successfully refreshed from Google Patents.
US3786282A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Radiation hardened flip flop
Assignee: Raytheon Co
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Filing: 1971-06-16
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Granted: 1974-01-15
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Expires: 1991-06-16
Abstract
Abstract A semiconductor flip flop capable of operating before, during and after an ionizing radiation environment. The radiation hardening is achieved by use of a capacitive memory in the cross coupled feedback loop of the flip flop circuit to drive the flip flop back to its pre-irradiation state.
Inventors
- 👤 R Orndorff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:35
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0372
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
181 words
A radiation hardened flip flop having set and reset inputs and set and reset outputs comprising: a first gate means coupled to receive the set input and reset output of said flip flop for directly providing the set output; a second gate means coupled to receive the reset input and the set output of said flip flop for directly providing the reset output; first and second resistors interconnected in series circuit relationship and coupled to feed said set output to said second gate means, including a first capacitor coupled between the common interconnection of said first and second resistors and a reference voltage level for retaining the set output voltage of said flip flop during the presence of an ionizing radiation environment; third and fourth resistors interconnected in series circuit relationship and coupled to feed said reset output to said first gate means, including a second capacitor coupled between the common interconnection of said third and fourth resistors and said reference voltage level for retaining the reset output voltage of said flip flop during the presence of an ionizing radiation environment.
Claim 2
Dependent Claim
181 words
A radiation hardened flip flop having set and reset inputs and set and reset outputs comprising: a first gate means coupled to receive the set input and reset output of said flip flop for directly providing the set output; a second gate means coupled to receive the reset input and the set output of said flip flop for directly providing the reset output; first and second resistors interconnected in series circuit relationship and coupled to feed said set output to said second gate means, including a first capacitor coupled between the common interconnection of said first and second resistors and a reference voltage level for retaining the set output voltage of said flip flop during the presence of an ionizing radiation environment; third and fourth resistors interconnected in series circuit relationship and coupled to feed said reset output to said first gate means, including a second capacitor coupled between the common interconnection of said third and fourth resistors and said reference voltage level for retaining the reset output voltage of said flip flop during the presence of an ionizing radiation environment.
Claim 3
Dependent Claim
23 words
A radiation hardened flip flop as claimed in claim 1 wherein said first gate means and said second gate means are NAND gates.
Claim 4
Dependent Claim
19 words
A radiation hardened flip flop as claimed in claim 1 wherein saiD reference voltage level is ground voltage level.
Claim 5
Dependent Claim
199 words
A radiation hardened flip flop having set and reset inputs and set and reset outputs comprising: a first gate means coupled to directly receive the set input and the reset output of said flip flop and coupled to provide the set output; a second gate means coupled to directly receive the reset input and the set output of said flip flop and coupled to provide the reset output; first and second resistors interconnected in series circuit relationship and coupled to feed the output of said first gate means to the set output of said flip flop, including a first capacitor coupled between the common interconnection of said first and second resistors and a reference voltage level for retaining the set output voltage of said flip flop during the presence of an ionizing radiation environment; third and fourth resistors interconnected in series circuit relationship and coupled to feed the output of said second gate means to the reset output of said flip flop, including a capacitor coupled between the common interconnection of said third and fourth resistors and a reference voltage level for retaining the reset output voltage of said flip flop during the presence of an ionizing radiation environment.
Claim 6
Dependent Claim
199 words
A radiation hardened flip flop having set and reset inputs and set and reset outputs comprising: a first gate means coupled to directly receive the set input and the reset output of said flip flop and coupled to provide the set output; a second gate means coupled to directly receive the reset input and the set output of said flip flop and coupled to provide the reset output; first and second resistors interconnected in series circuit relationship and coupled to feed the output of said first gate means to the set output of said flip flop, including a first capacitor coupled between the common interconnection of said first and second resistors and a reference voltage level for retaining the set output voltage of said flip flop during the presence of an ionizing radiation environment; third and fourth resistors interconnected in series circuit relationship and coupled to feed the output of said second gate means to the reset output of said flip flop, including a capacitor coupled between the common interconnection of said third and fourth resistors and a reference voltage level for retaining the reset output voltage of said flip flop during the presence of an ionizing radiation environment.
Claim 7
Dependent Claim
23 words
A radiation hardened flip flop as claimed in claim 4 wherein said first gate means and said second gate means are NAND gates.
Claim 8
Dependent Claim
19 words
A radiation hardened flip flop as claimed in claim 4 wherein said reference voltage level is ground voltage level.
Claim 9
Dependent Claim
275 words
A radiation hardened flip flop circuit comprising: a first flip flop coupled to receive a set input, a reset input and a clock input for providing a set output in response to the set input and the clock input and for providing a reset output in response to the reset input and the clock input; a first capacitive voltage storage means coupled to receive the set output of said first flip flop for retaining the output voltage of the set output during the presence of an ionizing radiation environment, a second capacitive voltage storage means coupled to receive the reset output of said first flip flop for retaining the output voltage of the reset output during the presence of an ionizing radiation environment; gate means coupled to receive the clock input for providing an inverted clock signal; a second flip flop coupled to receive the set output and reset output of said first flip flop and the inverted clock signal of said gate means for providing a set output in response to the set output of said first flip flop and the inverted clock signal and for providing a reset output in response to the reset output of said first flip flop and the inverted clock signal; a third capacitive voltage storage means coupled to receive the set output of said second flip flop for retaining the output voltage of the set output during the presence of an ionizing radiation environment; a fourth capacitive voltage storage means coupled to receive the reset output of said second flip flop for retaining the output voltage of the reset output during the presence of an ionizing radiation environment.
Claim 10
Dependent Claim
275 words
A radiation hardened flip flop circuit comprising: a first flip flop coupled to receive a set input, a reset input and a clock input for providing a set output in response to the set input and the clock input and for providing a reset output in response to the reset input and the clock input; a first capacitive voltage storage means coupled to receive the set output of said first flip flop for retaining the output voltage of the set output during the presence of an ionizing radiation environment, a second capacitive voltage storage means coupled to receive the reset output of said first flip flop for retaining the output voltage of the reset output during the presence of an ionizing radiation environment; gate means coupled to receive the clock input for providing an inverted clock signal; a second flip flop coupled to receive the set output and reset output of said first flip flop and the inverted clock signal of said gate means for providing a set output in response to the set output of said first flip flop and the inverted clock signal and for providing a reset output in response to the reset output of said first flip flop and the inverted clock signal; a third capacitive voltage storage means coupled to receive the set output of said second flip flop for retaining the output voltage of the set output during the presence of an ionizing radiation environment; a fourth capacitive voltage storage means coupled to receive the reset output of said second flip flop for retaining the output voltage of the reset output during the presence of an ionizing radiation environment.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-14 | 1977-07-16 | 1978-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-14 | 1981-07-16 | 1982-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-14 | 1985-07-16 | 1986-01-15 | $7700.00 | Window Closed / Lapsed |