Rfi-protected flip-flop

Claim 2

An RFI-protected flip-flop combination wherein a pair of inverting type amplifying devices are cross-coupled from the output of each to the input circuit of the other to form a pair of cross-coupling loops; the improvement comprising: a pair of capacitors each coupled between the output and input circuit of a different one of the inverter devices to provide regenerative feedback of RFI noise spikes; level setting means included in the input circuit of each of said devices; a first gating element included in the input circuit of each of said devices; and a second gating element included in each cross-coupling loop for forming a gating circuit with said first gating element.

Claim 3

The invention according to claim 1 wherein each capacitor is coupled to the junction of the associated level setting means and gating circuit.

Claim 4

The invention according to claim 2 wherein the pair of amplifying devices is a pair of bipolar transistors having collector circuits and base circuits corresponding to said output and input circuits, respectively.

Claim 5

The invention according to claim 3 wherein the gating elements are unidirectional conducting devices.

Claim 6

A noise insensitive storage circuit comprising, in combination: first and second inverters, each having an input terminal and an output terminal; means for cross-coupling the input terminal of each invertEr to the output terminal of the other to form first and second cross-coupling paths; first and second level setting means, the first included in the first cross-coupling path and the second included in the second cross-coupling path; and means responsive to a noise pulse received at an output terminal of either one of said inverters, of a polarity and amplitude normally sufficient to change the storage state of said storage circuit, for regeneratively coupling said pulse via the level setting means of said inverter to the input terminal of said inverter for preventing said storage circuit from changing state.

Claim 7

A noise insensitive storage circuit comprising, in combination: first and second inverters, each having an input terminal and an output terminal; means for cross-coupling the input terminal of each invertEr to the output terminal of the other to form first and second cross-coupling paths; first and second level setting means, the first included in the first cross-coupling path and the second included in the second cross-coupling path; and means responsive to a noise pulse received at an output terminal of either one of said inverters, of a polarity and amplitude normally sufficient to change the storage state of said storage circuit, for regeneratively coupling said pulse via the level setting means of said inverter to the input terminal of said inverter for preventing said storage circuit from changing state.

Claim 8

The combination claimed in claim 5, wherein each cross-coupling path comprises a diode in series with a level setting means, each diode being poled to conduct current in the forward direction from an input terminal through a level setting means through said diode and through an inverter, and wherein said means responsive to a noise pulse comprises first and second capacitors, the first connected between the output terminal of said first inverter and the connection between the diode and level shifting means leading to the input terminal of said first inverter, and the second connected between the output terminal of the second inverter and the connection between the diode and level shifting means leading to the input terminal of said second inverter.

Claim 9

In combination: a flip-flop including two amplifiers, each having a control electrode and an output electrode, and including a signal transmission path between the output electrode of each amplifier and the control electrode of the other amplifier, each such path comprising an impedance in series with a voltage level shifting circuit and a circuit for reducing the sensitivity of said flip-flop to noise spikes comprising two regenerative feedback paths, one connected between the output electrode of one amplifier and the connection between the impedance and level shifting circuit leading to the control electrode of said one amplifier, and the other connected between the output electrode of the other amplifier and the connection between the impedance and level shifting circuit leading to the control electrode of said other amplifier.

Claim 10

In combination: a flip-flop including two amplifiers, each having a control electrode and an output electrode, and including a signal transmission path between the output electrode of each amplifier and the control electrode of the other amplifier, each such path comprising an impedance in series with a voltage level shifting circuit and a circuit for reducing the sensitivity of said flip-flop to noise spikes comprising two regenerative feedback paths, one connected between the output electrode of one amplifier and the connection between the impedance and level shifting circuit leading to the control electrode of said one amplifier, and the other connected between the output electrode of the other amplifier and the connection between the impedance and level shifting circuit leading to the control electrode of said other amplifier.

Claim 11

The combination as set forth in claim 7, further including a circuit coupled to each feedback path for permitting the discharge of any charge which tends to accumulate in said discharge path, each such circuit having a long discharge time constant relative to the duration of a noise spike.

Claim 12

The combination as set forth in claim 7, wherein each impedance comprises a diode and each feedback path comprises a capacitor, and further including a resistive discharge path connected across each capacitor having a value such that the resistor-capacitor discharge time-constant is relatively long compared to the duration of a noise spike.