Dielectric strip isolation for jfet or mesfet depletion-mode bucket-brigade circuit

Claim 2

A monolithic integrated circuit of the bucket-brigade type utilizing depletion-mode field-effect transistors of the reversebiased junction gate type and comprising a common substrate fabricated of an electrically insulating or lightly doped semiconductor material of a first conductivity type, an epitaxial layer of a semiconductor material of a second conductivity type opposite of the first type and formed over a major surface of said substrate and in contact therewith, a plurality of spaced-apart heavily doped first semiconductor regions of the second conductivity type diffused in the epitaxial layer, said first doped regions forming the source and drain electrodes of adjacent depletion-mode type field effect transistors coupled longitudinally in series circuit relationship through the epitaxial layer due to the first doped regions forming both the drain electrodes of individual transistors and the source electrodes of the next successively coupled transistors, a thin dielectric layer formed over said epitaxial layer and in contact therewith and provided with holes therethrough aligned with gate electrode regions located in the epitaxial layer between the source and drain electrodes of each transistor, the gate electrode regions being isolated from said substrate and from each other, a plurality of narrowly spaced-apart metal layers formed over said dielectric layer and in contact therewith and adapted for connection of successive metal layers to alternate outputs of a two-phase digital clock generator, said metal layers each having a relatively large surface area compared to the narrow spacing area between adjacent metal layers, said metal layers having first end portions in contact with the gate electrode regions through the holes provided in said dielectric layer, said metal layers overlapping the drain electrode portions of the firsT doped regions and separated therefrom by said dielectric layer to form therewith metal-oxide-semiconductor (MOS) capacitors connected between the drain and gate electrodes of the transistors and thereby forming in combination with the transistors a single row of a plurality of serially connected bucket-brigade stages in monolithic integrated circuit form, the capacitors providing temporary storage sites for electric charge packets representing information that is caused to propagate through the bucketbrigade circuit by charge transfer through the serially coupled source-to-drain transistor channels of the bucket-brigade stages in response to the transistors being alternately and successively rendered conducting and nonconducting as a result of the application of two-phase clock pulses from the outputs of the digital clock, and dielectric means disposed only along two opposite sides of said epitaxial layer and in contact with the major surface of said substrate for defining the two side boundaries of the series coupled source-to-drain transistor channels and capacitor storage sites so as to allow the transfer of electric charge packets between adjacent capacitor storage sites to occur across the entire width of the defined source-to-drain channels and preventing any undesired coupling of the charge packets at any time, the gate electrode regions extending the entire width defined by said dielectric means so as to substantially increase the transconductance of the transistor devices and also to substantially increase the packing density for a given area of the substrate as compared to conventional diffusion isolation or ring structure isolation of JFET or MESFET devices.

Claim 3

The monolithic integrated bucket-brigade circuit set forth in claim 1 wherein said common substrate comprises a p conductivity type semiconductor material, said epitaxial layer comprises an n conductivity type semiconductor material, and said heavily doped first semiconductor regions comprise an n conductivity type semiconductor material.

Claim 4

The monolithic integrated bucket-brigade circuit set forth in claim 1 wherein a plurality of spaced-apart heavily doped second semiconductor regions of the first conductivity type diffused in the epitaxial layer in the source-to-drain channels to form the gate electrode regions therein whereby the transistors are of the JFET type, the plurality of heavily doped second semiconductor regions being one less than the plurality of the heavily doped first semiconductor regions.

Claim 5

The monolithic integrated bucket-brigade circuit set forth in claim 1 wherein the gate electrode regions are the portions of the epitaxial layer in the source-to-drain channels over-lapped by the holes provided through said dielectric layer whereby the transistors are of the MESFET type.

Claim 6

The monolithic integrated bucket-brigade circuit set forth in claim 1 wherein said dielectric means are strips of a dielectric material formed over the major surface of said common substrate and disposed along and in contact with the sides of the source-to-drain transistor channels and capacitor storage sites.

Claim 7

The monolithic integrated bucket-brigade circuit wet forth in claim 5 wherein said metal layers also overlap said dielectric strips and are in contact therewith, said dielectric strips oriented substantially perpendicular to said metal layers.

Claim 8

The monolithic integrated bucket-brigade circuit set forth in claim wherein said dielectric means are oxidized portions of said epitaxial layer in the regions along and in contact with the sides of the source-to-drain transistor channels and capacitor storage sites.

Claim 9

The monolithic integrated bucket-brigade circuit set forth in claim 7 wherein said dielectric layer also overlaps the oxidized portions of said epitaxial layer, the oxidized portions of said epitaxial layer oriented substantially perpendicular to said metal layers.

Claim 10

The monolithic integratEd bucket brigade circuit set forth in claim 2 and further comprising a p diffused channel stopper formed at the two interfaces of said dielectric means and said substrate for preventing inversion of the p -type substrate material to the n-type.

Claim 11

A monolithic integrated circuit of the bucket-brigade type uitilizing depletion-mode field-effect transistors of the reverse-biased junction gate type and comprising a common substrate fabricated of an electrically insulating or lightly doped semiconductor material of a first conductivity type, a plurality of spaced-apart parallel oriented epitaxial layers of a semiconductor material of a second conductivity type opposite of the first type and formed over a major surface of said substrate and in contact therewith, a plurality of spaced-apart heavily doped first semiconductor regions of the second conductivity type diffused in the epitaxial layers and arranged in a single row in each epitaxial layer, said first doped regions forming the source and drain electrodes of adjacent depletion-mode type field effect transistors coupled longitudinally in series circuit relationship in each row thereof through the common epitaxial layer due to the first doped regions forming both the drain electrodes of individual transistors and the source electrodes of the next successively coupled transistors, a thin dielectric layer formed over said epitaxial layers and in contact therewith and provided with holes therethrough aligned with gate electrode regions located in the epitaxial layers between the source and drain electrodes of each transistor, the gate electrode regions being isolated from said substrate and from each other, a plurality of narrowly spaced-apart parallel metal layers formed over said dielectric layer and in contact therewith and adapted for connection of successive metal layers to alternate outputs of a two-phase digital clock generator, said metal layers each having a relatively large surface area compared to the narrow spacing area between adjacent metal layers, said metal layers oriented substantially perpendicular to said epitaxial layers and having first end portions in contact with the gate electrode regions through the holes provided in said dielectric layer, said metal layers overlapping the drain electrode portions of the first doped regions and separated therefrom by said dielectric layer to form therewith metal-oxide-semiconductor (MOS) capacitors connected between the drain and gate electrodes of the transistors and thereby forming in combination with the transistors a plurality of rows and columns of bucket-brigade stages in monolithic integrated circuit form, the bucket-brigade stages being serially connected in each row and the number of rows being equal to the plurality of epitaxial layers, the number of columns being equal to the plurality of metal layers, the capacitors providing temporary storage sites for electric charge packets representing information that is caused to propagate through the bucket-brigade circuit by charge transfer through the serially coupled source-to-drain transistor channels of the bucket-brigade stages in response to the transistors being alternately and successively rendered conducting and nonconducting as a result of the application of two-phase clock pulses from the outputs of the digital clock, and dielectric means disposed only along two opposite sides of each said epitaxial layer and in contact with said substrate for defining the two side boundaries of the series coupled source-to-drain transistor channels and capacitor storage sites so as to allow the transfer of electric charge packets between adjacent capacitor storage sites to occur across the entire width of the defined source-to-drain channels and preventing any undesired coupling of the charge packets at any time, the gate electrode regions extending the entire width defined by said dielectric means so as to substantially increase the transconductance of the transistor deVices, and also to substantially increase the packing density for a given area of the substrate as compared to conventional diffusion isolation or ring structure isolation of JFET or MESFET devices.

Claim 12

A monolithic integrated circuit of the bucket-brigade type uitilizing depletion-mode field-effect transistors of the reverse-biased junction gate type and comprising a common substrate fabricated of an electrically insulating or lightly doped semiconductor material of a first conductivity type, a plurality of spaced-apart parallel oriented epitaxial layers of a semiconductor material of a second conductivity type opposite of the first type and formed over a major surface of said substrate and in contact therewith, a plurality of spaced-apart heavily doped first semiconductor regions of the second conductivity type diffused in the epitaxial layers and arranged in a single row in each epitaxial layer, said first doped regions forming the source and drain electrodes of adjacent depletion-mode type field effect transistors coupled longitudinally in series circuit relationship in each row thereof through the common epitaxial layer due to the first doped regions forming both the drain electrodes of individual transistors and the source electrodes of the next successively coupled transistors, a thin dielectric layer formed over said epitaxial layers and in contact therewith and provided with holes therethrough aligned with gate electrode regions located in the epitaxial layers between the source and drain electrodes of each transistor, the gate electrode regions being isolated from said substrate and from each other, a plurality of narrowly spaced-apart parallel metal layers formed over said dielectric layer and in contact therewith and adapted for connection of successive metal layers to alternate outputs of a two-phase digital clock generator, said metal layers each having a relatively large surface area compared to the narrow spacing area between adjacent metal layers, said metal layers oriented substantially perpendicular to said epitaxial layers and having first end portions in contact with the gate electrode regions through the holes provided in said dielectric layer, said metal layers overlapping the drain electrode portions of the first doped regions and separated therefrom by said dielectric layer to form therewith metal-oxide-semiconductor (MOS) capacitors connected between the drain and gate electrodes of the transistors and thereby forming in combination with the transistors a plurality of rows and columns of bucket-brigade stages in monolithic integrated circuit form, the bucket-brigade stages being serially connected in each row and the number of rows being equal to the plurality of epitaxial layers, the number of columns being equal to the plurality of metal layers, the capacitors providing temporary storage sites for electric charge packets representing information that is caused to propagate through the bucket-brigade circuit by charge transfer through the serially coupled source-to-drain transistor channels of the bucket-brigade stages in response to the transistors being alternately and successively rendered conducting and nonconducting as a result of the application of two-phase clock pulses from the outputs of the digital clock, and dielectric means disposed only along two opposite sides of each said epitaxial layer and in contact with said substrate for defining the two side boundaries of the series coupled source-to-drain transistor channels and capacitor storage sites so as to allow the transfer of electric charge packets between adjacent capacitor storage sites to occur across the entire width of the defined source-to-drain channels and preventing any undesired coupling of the charge packets at any time, the gate electrode regions extending the entire width defined by said dielectric means so as to substantially increase the transconductance of the transistor deVices, and also to substantially increase the packing density for a given area of the substrate as compared to conventional diffusion isolation or ring structure isolation of JFET or MESFET devices.

Claim 13

The monolithic integrated bucket-brigade circuit set forth in claim 10 wherein said common substrate comprises a p conductivity type semiconductor material, said epitaxial layers comprise an n conductivity type semiconductor material, and said heavily doped first semiconductor regions comprise an n conductivity type semiconductor material.

Claim 14

The monolithic integrated bucket-brigade circuit set forth in claim 10 wherein a plurality of spaced-apart heavily doped second semiconductor regions of the first conductivity type diffused in the epitaxial layers in the source-to-drain channels to form the gate electrode regions therein whereby the transistors are of the JFET type, the plurality of heavily doped second semiconductor regions being one less than the plurality of the heavily doped first semiconductor regions.

Claim 15

The monolithic integrated bucket-brigade circuit set forth in claim 10 wherein the gate electrode regions are the portions of the epitaxial layers in the source-to-drain channels overlapped by the holes provided through said dielectric layer whereby the transistors are of the MESFET type.

Claim 16

The monolithic integrated bucket-brigade circuit set forth in claim 10 wherein said dielectric means are a plurality of parallel strips of a dielectric material formed over the major surface of said common substrate and disposed along and in contact with the sides of the source-to-drain transistor channels and capacitor storage sites and providing the spacing between adjacent epitaxial layers.

Claim 17

The monolithic integrated bucket-brigade circuit set forth in claim 14 wherein said metal layers also overlap said dielectric strips and are in contact therewith, said dielectric strips oriented substantially perpendicular to said metallized layers.

Claim 18

The monolithic integrated bucket-brigade circuit set forth in claim 10 wherein said dielectric means are a plurality of parallel oxidized portions of said epitaxial layers in the regions along and in contact with the sides of the source-to-drain transistor channels and capacitor storage sites and providing the spacing between adjacent epitaxial layers.

Claim 19

The monolithic integrated bucket-brigade circuit set forth in claim 16 wherein said dielectric layer also overlaps the oxidized portions of said epitaxial layers, the oxidized portions of said epitaxial layers oriented substantially perpendicular to said metal layers.

Claim 20

The monolithic integrated bucket-brigade circuit set forth in claim 11 wherein the substrate semiconductor material is silicon, the epitaxial layer material is silicon, and the dielectric layer material is silicon dioxide.

Claim 21

The monolithic integrated bucket-brigade circuit set forth in claim 18 wherein the metal layer material is aluminum.

Claim 22

The monolithic integrated bucket-brigade circuit set forth in claim 11 and further comprising a p diffused channel stopper formed at each interface of said dielectric means and said substrate for preventing inversion of the p -type substrate to n-type.