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US3783307A Expired / Lapsed US ⏱️ 0.0 years remaining

Analog transmission gate

Assignee: Northrop Grumman Space and Mission Systems Corp
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Filing: 1972-01-03
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Granted: 1974-01-01
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Expires: 1992-01-03
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Abstract

Abstract A transistor switching network, responding to a logic input, switches current selectively into one of a number of nodes, each node connecting a pair of bipolar transistors coupled differentially in a unity gain amplifier circuit. From a number of analog input signals applied to the differentially connected transistor pairs, only the one coupled to the selected node will produce an output from the voltage follower circuit. Conversely, a single analog input signal may be gated selectively to any one of a number of output terminals.

Inventors

  • 👤 D Breuer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 15:01
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6257; H03K17/6264; H03F; H03F3/00; H03F3/72; H03K17/6285; H03K17/6292

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 186 words
An analog transmission gate, comprising: a unity gain amplifier circuit including a plurality of pairs of transistors, with the transistors of each pair connected directly together differentially without any intervening elements at a separate node point, each of said transistors having an input circuit and an output circuit, and a feedback loop between the output and input circuits of one of the transistors of each pair; a plurality of signal terminals on one side of said amplifier circuit and only one signal terminal on the other side of said amplifier circuit; and a constant current means including a commutating circuit means and a single constant current source in which said commutating circuit means is coupled between said constant current source and said node points for feeding current from said constant current source; to each of said node points selectively one at a time so that at any one time the signal appearing at said one signal terminal is the same as the signal appearing at only the one of the plurality of signal terminals that is coupled to the amplifier circuit through the selected node point.
Claim 2
Dependent Claim 186 words
An analog transmission gate, comprising: a unity gain amplifier circuit including a plurality of pairs of transistors, with the transistors of each pair connected directly together differentially without any intervening elements at a separate node point, each of said transistors having an input circuit and an output circuit, and a feedback loop between the output and input circuits of one of the transistors of each pair; a plurality of signal terminals on one side of said amplifier circuit and only one signal terminal on the other side of said amplifier circuit; and a constant current means including a commutating circuit means and a single constant current source in which said commutating circuit means is coupled between said constant current source and said node points for feeding current from said constant current source; to each of said node points selectively one at a time so that at any one time the signal appearing at said one signal terminal is the same as the signal appearing at only the one of the plurality of signal terminals that is coupled to the amplifier circuit through the selected node point.
Claim 3
Dependent Claim 35 words
The invention according to claim 1, wherein said plurality of signal terminals are located at the input side of said amplifier circuit and said only one signal terminal is located at the output side thereof.
Claim 4
Dependent Claim 181 words
The invention according to claim 2 and comprising further: said plurality of pairs of transistors comprise a first set of transistors and a second set of transistors; in said first set of transistors the collectors thereof are connected in common with a first junction, and each base is connected to a separate input signal terminal; in said second set of transistors, the collectors are connected in common with a second junction, and the bases are connected in common with a single output signal terminal; each of said node points forming a common connection between the emitter of one transistor from said first set and the emitter of one transistor from said second set; a positive voltage supply connected to said first junction; a resistor connected between said first and second junctions; a negative voltage supply; a resistor connected between said negative voltage supply and said output signal terminal; and an additional transistor forming an emitter follower and having its base connected to said second junction, its collector connected to said first junction, and its emitter connected to said output signal terminal.
Claim 5
Dependent Claim 55 words
The invention according to claim 1, wherein said commutating circuit means includes: a transistor switching circuit connected between said constant current source and said node points and selectively responsive to distinct logic input signals to conduct said constant current to each one of said node points selectively as determined by a different logic iNput signal.
Claim 6
Dependent Claim 138 words
The invention according to claim 1, wherein said commutating circuit means comprises: a plurality of stages of differentially connected transistor circuits, each stage of which includes a pair of transistors having their emitters connected directly in common to form a current input terminal for receiving current from said constant current source, one transistor of each pair having its base serving as a control terminal for receiving a logic input signal voltage, the other transistor of each pair having its base connected to a potential other than said logic input signal voltage, the first stage of said differential connected transistor pairs having their collectors connected separately to a common emitter input terminal of a succeeding stage, and the final stages of said differentially connected transistor pairs having their collectors connected separately to a different one of said node points.
Claim 7
Dependent Claim 149 words
An analog transmission gate, comprising: a unity gain amplifier circuit including a plurality of pairs of transistors, with the transistors of each pair connected directly together differentially at a separate node point, each of said transistors having an input circuit and an output circuit, and a feedback loop between the output and input circuits of one of the transistors of each pair; a plurality of signal terminals on the output side of said amplifier circuit and only one signal terminal on the input side of said amplifier circuit; and means for feeding a constant current to each of said node points selectively one at a time so that at any one time the signal appearing at said one signal terminal is the same as the signal appearing at only the one of the plurality of signal terminals that is coupled to the amplifier circuit through the selected node point.
Claim 8
Dependent Claim 149 words
An analog transmission gate, comprising: a unity gain amplifier circuit including a plurality of pairs of transistors, with the transistors of each pair connected directly together differentially at a separate node point, each of said transistors having an input circuit and an output circuit, and a feedback loop between the output and input circuits of one of the transistors of each pair; a plurality of signal terminals on the output side of said amplifier circuit and only one signal terminal on the input side of said amplifier circuit; and means for feeding a constant current to each of said node points selectively one at a time so that at any one time the signal appearing at said one signal terminal is the same as the signal appearing at only the one of the plurality of signal terminals that is coupled to the amplifier circuit through the selected node point.
Claim 9
Dependent Claim 236 words
The invention according to claim 3, and comprising further: said plurality of pairs of transistors comprise a first set of transistors and a second set of transistors; in said first set of transistors, the bases thereof are connected in common and to a single input signal terminal, and the collectors thereof are connected in common with a first junction; a positive voltage supply connected to said first junction; in said second set of transistors, each base is connected to a separate one of said plurality of output signal terminals; each of said node points forming a common connection between the emitter of one transistor from said first set and the emitter of one transistor from said second set; a plurality of resistors, one for each transistor of said second set connected between the collector thereof and said first junction; a plurality of additional transistors, one in the collector-base circuit of each transistor of said second set and forming an emitter-follower therewith, each additional transistor having its base connected to the collector of the respective transistor of said second set, its emitter connected to a separate one of said plurality of output signal terminals and its collector connected to said first junction; a negative voltage supply; and a plurality of pull down resistors, one for each of said additional transistors connected between said negative voltage supply and a separate one of said plurality of output signal terminals.
Claim 10
Dependent Claim 28 words
The invention according to claim 5, wherein said first set of transistors is formed by a multiple emitter coalesced transistor having a common base and a common collector.

References Cited (Backward Citations)

GB1100262A Cited
US3351782A Cited
US3522450A Cited
US3539831A Cited
US3518458A Cited
US3614478A Cited
US3719830A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-12-31 1977-07-02 1978-01-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-12-31 1981-07-02 1982-01-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-12-31 1985-07-02 1986-01-01 $7700.00 Window Closed / Lapsed

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