Patent US3781828A successfully refreshed from Google Patents.
US3781828A
Expired / Lapsed
US
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Three-dimensionally addressed memory
Assignee: International Business Machines Corp
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Filing: 1972-05-04
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Granted: 1973-12-25
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Expires: 1992-05-04
Abstract
Abstract An array of memory cells is provided with each cell having a word top line, a word bottom line and a pair of bit lines connected thereto. Either a standby voltage or a select voltage is applied to each of the lines, whereby any cell of the array may be selected by applying a select voltage to the two word lines and one or both bit lines connected to the cell. In one of the disclosed embodiments, the cells are arranged in columns and in groups of rows. Each of a plurality of word top drive lines is connected to all of the rows of the cells of a respective group to select any group of rows, each of a plurality of word bottom drive lines is connected to a respective row of cells in each of the groups to select one row of the selected group, and a plurality of pairs of bit lines are provided with each pair connected to the cells of a respective column to select one column and thereby one cell of the selected row. Each cell preferably comprises a cross-coupled pair of transistors each having a collector and first and second emitters. The word top lines are connected to the collector load impedances, the word bottom lines are connected to the first emitters, and the bit lines are connected to the second emitters.
Inventors
- 👤 S Platt
- 👤 J Pomeranz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:48
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
70 words
A memory cell comprising a pair of transistors each having a collector, a base, and first and second emitters, cross-coupling means connecting the base of each transistor to the collector of the other transistor, a pair of load impedances each connected to a respective collector, first addressing means connected to said load impedances, second addressing means connected to said first emitters, and third addressing means connected to said second emitters.
Claim 2
Dependent Claim
70 words
A memory cell comprising a pair of transistors each having a collector, a base, and first and second emitters, cross-coupling means connecting the base of each transistor to the collector of the other transistor, a pair of load impedances each connected to a respective collector, first addressing means connected to said load impedances, second addressing means connected to said first emitters, and third addressing means connected to said second emitters.
Claim 3
Dependent Claim
48 words
A memory cell as recited in claim 1 wherein said first addressing means comprises a word top line, said second addressing means comprises a word bottom line, and said third addressing means comprises a pair of bit lines each connected to a respective one of said second emitters.
Claim 4
Dependent Claim
48 words
A memory cell as recited in claim 2 and comprising a first decoder circuit and line driver connected to said word top line, a second decoder circuit and line driver connected to said word bottom line, and a decoder switch and sense amplifier connected to said bit lines.
Claim 5
Dependent Claim
87 words
A three-dimensionally addressed memory comprising an array of memory cells arranged in a plurality of vertical columns and a plurality of horizontal groups each including a plurality of horizontal rows, a plurality of pairs of bit lines with each pair connected to the cells of a respective column, a first plurality of word lines each connected to all of the rows of cells of a respective group, and a second plurality of word lines each connected to a respective row of cells of each of the groups.
Claim 6
Dependent Claim
87 words
A three-dimensionally addressed memory comprising an array of memory cells arranged in a plurality of vertical columns and a plurality of horizontal groups each including a plurality of horizontal rows, a plurality of pairs of bit lines with each pair connected to the cells of a respective column, a first plurality of word lines each connected to all of the rows of cells of a respective group, and a second plurality of word lines each connected to a respective row of cells of each of the groups.
Claim 7
Dependent Claim
76 words
A memory as recited in claim 4 and comprising a plurality of decoder switches each connected to a respective pair of bit lines, a sense amplifier connected to said decoder switches, a first plurality of decoder and line driver circuits each connected to a respective one of said first plurality of word lines, and a second plurality of decoder and line driver circuits each connected to a respective one of said second plurality of word lines.
Claim 8
Dependent Claim
96 words
A memory as recited in claim 4 wherein each of said cells comprises a pair of transistors each having a collector, a base, and first and second emitters, cross-coupling means connecting the base of each transistor to the collector of the other transistor, and a pair of load impedances each connected to a respective collector, one of said first plurality of word lines being connected to said load impedances, the respective pair of bit lines being connected to said first emitters, and one of said second plurality of word lines being connected to said second emitters.
Claim 9
Dependent Claim
76 words
A memory as recited in claim 6 and comprising a plurality of decoder switches each connected to a respective pair of bit lines, a sense amplifier connected to said decoder switches, a first plurality of decoder and line driver circuits each connected to a respective one of said first plurality of word lines, and a second plurality of decoder and line driver circuits each connected to a respective one of said second plurality of word lines.
Claim 10
Dependent Claim
147 words
A memory comprising an array of memory cells arranged in a plurality of vertical columns and a plurality of horizontal groups each including a plurality of horizontal rows, first addressing means for partially selecting the cells of a selected group, second addressing means for partially selecting the cells of a selected column, and third addressing means for partially selecting the cells of a selected row of the selected group, each of said cells comprising a pair of transistors each having a collector, a base, and first and second emitters, cross-coupling means connecting the base of each transistor to the collector of the other transistor, and a pair of load impedances each connected to a respective collector, said first addressing means being connected to said load Impedances, said second addressing means being connected to said first emitters, and said third addressing means being connected to said second emitters.
Claim 11
Dependent Claim
147 words
A memory comprising an array of memory cells arranged in a plurality of vertical columns and a plurality of horizontal groups each including a plurality of horizontal rows, first addressing means for partially selecting the cells of a selected group, second addressing means for partially selecting the cells of a selected column, and third addressing means for partially selecting the cells of a selected row of the selected group, each of said cells comprising a pair of transistors each having a collector, a base, and first and second emitters, cross-coupling means connecting the base of each transistor to the collector of the other transistor, and a pair of load impedances each connected to a respective collector, said first addressing means being connected to said load Impedances, said second addressing means being connected to said first emitters, and said third addressing means being connected to said second emitters.
Claim 12
Dependent Claim
147 words
A memory comprising an array of memory cells arranged in a plurality of vertical columns and a plurality of horizontal groups each including a plurality of horizontal rows, first addressing means for partially selecting the cells of a selected group, second addressing means for partially selecting the cells of a selected column, and third addressing means for partially selecting the cells of a selected row of the selected group, each of said cells comprising a pair of transistors each having a collector, a base, and first and second emitters, cross-coupling means connecting the base of each transistor to the collector of the other transistor, and a pair of load impedances each connected to a respective collector, said third addressing means being connected to said load impedances, said second addressing means being connected to said first emitters, and said first addressing means being connected to said second emitters.
Claim 13
Dependent Claim
147 words
A memory comprising an array of memory cells arranged in a plurality of vertical columns and a plurality of horizontal groups each including a plurality of horizontal rows, first addressing means for partially selecting the cells of a selected group, second addressing means for partially selecting the cells of a selected column, and third addressing means for partially selecting the cells of a selected row of the selected group, each of said cells comprising a pair of transistors each having a collector, a base, and first and second emitters, cross-coupling means connecting the base of each transistor to the collector of the other transistor, and a pair of load impedances each connected to a respective collector, said third addressing means being connected to said load impedances, said second addressing means being connected to said first emitters, and said first addressing means being connected to said second emitters.
Claim 14
Dependent Claim
73 words
A memory as recited in claim 11 wherein said cells are arranged in columns and in groups of rows, a plurality of said first lines each connected to all of the rows of cells of a respective group, a plurality of said second lines each connected to a respective row of cells in each of the groups, and a plurality of said third lines each connected to the cells of a respective column.
Claim 15
Dependent Claim
177 words
A memory comprising an array of memory cells, each cell having at least first, second and third lines connected thereto, means for applying either a standby voltage or a select voltage to each of said three lines, whereby any cell of the array may be selected by applying a select voltage to all three lines connected to said cell, said cells are arranged in columns and in groups of rows, a plurality of said first lines each connected to all of the rows of cells of a respective group, a plurality of said second lines each connected to a respective row of cells in each of the groups, a plurality of said third lines each connected to the cells of a respective column, each of said cells comprising a transistor having a collector and first and second emitters, said first lines being connected to the collectors of the respective cells, said second lines being connected to the first emitters of the respective cells, and said third lines being connected to the second emitters of the respective cell.
Claim 16
Dependent Claim
177 words
A memory comprising an array of memory cells, each cell having at least first, second and third lines connected thereto, means for applying either a standby voltage or a select voltage to each of said three lines, whereby any cell of the array may be selected by applying a select voltage to all three lines connected to said cell, said cells are arranged in columns and in groups of rows, a plurality of said first lines each connected to all of the rows of cells of a respective group, a plurality of said second lines each connected to a respective row of cells in each of the groups, a plurality of said third lines each connected to the cells of a respective column, each of said cells comprising a transistor having a collector and first and second emitters, said first lines being connected to the collectors of the respective cells, said second lines being connected to the first emitters of the respective cells, and said third lines being connected to the second emitters of the respective cell.
Claim 17
Dependent Claim
177 words
A memory comprising an array of memory cells, each cell having at least first, second and third lines connected thereto, means for applying either a standby voltage or a select voltage to each of said three lines, whereby any cell of the array may be selected by applying a select voltage to all three lines connected to said cell, said cells are arranged in columns and in groups of rows, a plurality of said first lines each connected to all of the rows of cells of a respective group, a plurality of said second lines each connected to a respective row of cells in each of the groups, a plurality of said third lines each connected to the cells of a respective column, each of said cells comprising a transistor having a collector and first and second emitters, said second lines being connected to the collectors of the respective cells, said first lines being connected to the first emitters of the respective cells, and said third lines being connected to the second emitters of the respective cells.
Claim 18
Dependent Claim
177 words
A memory comprising an array of memory cells, each cell having at least first, second and third lines connected thereto, means for applying either a standby voltage or a select voltage to each of said three lines, whereby any cell of the array may be selected by applying a select voltage to all three lines connected to said cell, said cells are arranged in columns and in groups of rows, a plurality of said first lines each connected to all of the rows of cells of a respective group, a plurality of said second lines each connected to a respective row of cells in each of the groups, a plurality of said third lines each connected to the cells of a respective column, each of said cells comprising a transistor having a collector and first and second emitters, said second lines being connected to the collectors of the respective cells, said first lines being connected to the first emitters of the respective cells, and said third lines being connected to the second emitters of the respective cells.
Claim 19
Dependent Claim
120 words
A three-dimensionally addressed memory comprising an array of memory cells arranged in columns and in groups each including a plurality of rows, a plurality of word top lines each connected to the cells of a respective row, a plurality of word bottom lines each connected to the cells of a respective row, a Plurality of bit lines each connected to the cells of a respective column, a plurality of word top drive lines each connected to those word top lines connected to the cells of all of the rows of a respective group, and a plurality of word bottom drive lines each connected to those word bottom lines connected to a respective row of cells in each of the groups.
Claim 20
Dependent Claim
120 words
A three-dimensionally addressed memory comprising an array of memory cells arranged in columns and in groups each including a plurality of rows, a plurality of word top lines each connected to the cells of a respective row, a plurality of word bottom lines each connected to the cells of a respective row, a Plurality of bit lines each connected to the cells of a respective column, a plurality of word top drive lines each connected to those word top lines connected to the cells of all of the rows of a respective group, and a plurality of word bottom drive lines each connected to those word bottom lines connected to a respective row of cells in each of the groups.
Claim 21
Dependent Claim
68 words
A memory as recited in claim 13 and comprising a first plurality of decoder and line driver circuits each connected to a respective word top drive line, a second plurality of decoder and line driver circuits each connected to a respective word bottom drive line, a plurality of decoder switch circuits each connected to a respective bit line, and a sense amplifier connected to said decoder switch circuits.
Claim 22
Dependent Claim
119 words
A three-dimensionally addressed memory comprising an array of memory cells arranged in columns and in groups each including a plurality of rows, a plurality of word top lines each connected to the cells of a respective row, a plurality of word bottom lines each connected to the cells of a respective row, a plurality of bit lines each connected to the cells of a respective column, a plurality of word top drive lines each connected to those word top lines connected to a respective row of cells in each of the groups, and a plurality of word drive lines each connected to those word bottom lines connected to the cells of all of the rows of a respective group.
Claim 23
Dependent Claim
119 words
A three-dimensionally addressed memory comprising an array of memory cells arranged in columns and in groups each including a plurality of rows, a plurality of word top lines each connected to the cells of a respective row, a plurality of word bottom lines each connected to the cells of a respective row, a plurality of bit lines each connected to the cells of a respective column, a plurality of word top drive lines each connected to those word top lines connected to a respective row of cells in each of the groups, and a plurality of word drive lines each connected to those word bottom lines connected to the cells of all of the rows of a respective group.
Claim 24
Dependent Claim
68 words
A memory as recited in claim 15 and comprising a first plurality of decoder and line driver circuits each connected to a respective word top drive line, a second plurality of decoder and line driver circuits each connected to a respective word bottom drive line, a plurality of decoder switch circuits each connected to a respective bit line, and a sense amplifier connected to said decoder switch circuits.
Claim 25
Dependent Claim
145 words
A memory cell comprising a pair of transistors each having a collector, a base, and first and second emitters, cross-coupling means connecting the base of each transistor to the collector of the other transistor, a pair of load impedances each connected to a respective collector, a word top line connected to said load impedances, a pair of bit lines connected respectively to said second emitters, a diode connected to said first emitters, a word bottom line connected to said diode, a resistor connected to said second emitters, a voltage source connected to said resistor, means for selectively applying either a select voltage or a standby voltage to said word top line, means for selectively applying either a select voltage or a standby voltage to said word bottom line, and means for selectively applying either a select voltage or a standby voltage to said bit lines.
Claim 26
Dependent Claim
145 words
A memory cell comprising a pair of transistors each having a collector, a base, and first and second emitters, cross-coupling means connecting the base of each transistor to the collector of the other transistor, a pair of load impedances each connected to a respective collector, a word top line connected to said load impedances, a pair of bit lines connected respectively to said second emitters, a diode connected to said first emitters, a word bottom line connected to said diode, a resistor connected to said second emitters, a voltage source connected to said resistor, means for selectively applying either a select voltage or a standby voltage to said word top line, means for selectively applying either a select voltage or a standby voltage to said word bottom line, and means for selectively applying either a select voltage or a standby voltage to said bit lines.
Claim 27
Dependent Claim
187 words
A three-dimensionally addressed memory comprising an array of memory cells each as recited in claim 11, said array of memory cells being arranged in a plurality of columns and a plurality of groups each including a plurality of rows, each of the word top lines being in common with and connected to all the cells of a respective row, each of the word bottom lines being in common with and connected to all the cells of a respective row, each of the pairs of bit lines being in common with and connected to all the cells of a respective column, a plurality of word top drive lines each connected to all of the word top lines connected to all of the rows of cells of a respective group, a plurality of word bottom drive lines each connected to the word bottom lines connected to a respective row of cells of each of the groups, a first plurality of line driver circuits each connected to a respective word top drive line, and a second plurality of line driver circuits each connected to a respective word bottom drive line.
Claim 28
Dependent Claim
187 words
A three-dimensionally addressed memory comprising an array of memoRy cells each as recited in claim 17, said array of memory cells being arranged in a plurality of columns and a plurality of groups each including a plurality of rows, each of the word top lines being in common with and connected to all the cells of a respective row, each of the word bottom lines being in common with and connected to all the cells of a respective rows, each of the pairs of bit lines being in common with and connected to all the cells of a respective column, a plurality of word bottom drive lines each connected to all of the word bottom lines connected to all of the rows of cells of a respective group, a plurality of word top drive lines each connected to the word top lines connected to a respective row of cells of each of the groups, a first plurality of line driver circuits each connected to a respective word top drive line, and a second plurality of line driver circuits each connected to a respective word bottom drive line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |