Memory system incorporating a memory cell and timing means on a single semiconductor substrate

Claim 2

A semi-conductor memory system for electrically storing information comprising memory cell array means for storing a plurality of bits of information formed on a monolithic semiconductor substrate, said array comprising a plurality of memory cells, each cell capable of storing a bit of information; address buffer means for receiving address information inputs and for providing an output representative of a selected address; decode means coupled to the output of said address means and to said memory cell array means for generating a signal to select the addressed portion of said memory cell array means; and timing generator means for generating a plurality of timing signals to control the operation of said array means; said timing generator means formed on said monolithic semi-conductor substrate containing said array means, said timing generator means providing said timing signals upon the receipt of an external clock signal.

Claim 3

The structure recited in claim 1, wherein a single external timing signal is received by said timing generator means.

Claim 4

The structure recited in claim 2, wherein said memory cell array means, said address means, said decode means and said timing generator means are formed on a single monolithic semi-conductor substrate.

Claim 5

The structure recited in claim 3, wherein said semiconductor memory system is an MOS dynamic memory system.

Claim 6

A structure recited in claim 4, wherein said memory cell of said memory array cell means employs three MOS transistors interconnected for selection through a single select line during reading and writing and interconnected to a single column line to allow transfer of information into and out of the cell, and interconnected to a single ground line shared between two adjacent columns of cells.

Claim 7

The structure recited in claim 5, wherein an intermediate voltage generator means is coupled to said decode means for providing a tri-state signal having a low level, an intermediate level and a high level, said intermediate level for enabling the reading of the selected portions of said memory cell array means and said high level enabling the writing and refreshing of said memory cell array means.

Claim 8

The structure recited in claim 1, including a timing cell means coUpled to said time generating means and said memory cell array means for determining the general characteristics of the memory cell means, and for adjusting the timing signals provided by the timing generator means.

Claim 9

The structure recited in claim 6, including a timing cell means coupled to said time generating means and said memory cell array means for determining the general characteristics of the memory cell means, and for adjusting the timing signals provided by the timing generator means.

Claim 10

The structure recited in claim 7, including a timing cell means coupled to said time generator means and said memory cell array means for determining the general characteristics of the memory cell means and for adjusting the timing signals provided by the time generator means.

Claim 11

A semiconductor memory system for electrically storing information comprising memory cell array means for storing a plurality of bits of information, said array means formed on a monolithic semiconductor substrate, and comprising a plurality of memory cells, each cell capable of storing a bit of information; address buffer means for receiving address information input and for providing an output signal representative of a selected address; decode means coupled to the output of said address means and to said memory cell array means for generating a signal to select the addressed portion of said memory cell array means; timing generator means for generating a plurality of timing signals to control the operation of said array means; said timing generator means formed on said monolithic semi-conductor substrate containing said array means, said timing generator means providing said timing signals upon the receipt of an external clock signal; and time compensating circuit means formed on said monolithic semiconductor substrate and coupled to said memory cell array means for compensating timing signals for variations in said devices formed on monolithic semiconductor substrate.

Claim 12

A semiconductor memory system for electrically storing information comprising memory cell array means for storing a plurality of bits of information, said array means formed on a monolithic semiconductor substrate, and comprising a plurality of memory cells, each cell capable of storing a bit of information; address buffer means for receiving address information input and for providing an output signal representative of a selected address; decode means coupled to the output of said address means and to said memory cell array means for generating a signal to select the addressed portion of said memory cell array means; timing generator means for generating a plurality of timing signals to control the operation of said array means; said timing generator means formed on said monolithic semi-conductor substrate containing said array means, said timing generator means providing said timing signals upon the receipt of an external clock signal; and time compensating circuit means formed on said monolithic semiconductor substrate and coupled to said memory cell array means for compensating timing signals for variations in said devices formed on monolithic semiconductor substrate.

Claim 13

The structure recited in claim 4 wherein said address buffer means includes a register for storing address information.