Patent US2387457A successfully refreshed from Google Patents.
Patent US3277098A successfully refreshed from Google Patents.
Patent US3778550A successfully refreshed from Google Patents.
US3778550A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for synchronizing clock signals to incoming data
Assignee: US Philips Corp
•
Filing: 1971-07-27
•
Granted: 1973-12-11
•
Expires: 1991-07-27
Abstract
Abstract A synchronizing device locally reproducing with very high precision the phase of a clock signal at the rhythm of which data are received, comprising two independent control circuits, one for correcting the frequency of the local oscillator, the other for correcting the phase of the local clock signal; in the phase correcting arrangement a device detecting the transition of the incoming data supplies pulses at the zero passages of the digital integrators, which pulses are filtered in a digital filter which produces phase-correction instructions to a correction device.
Inventors
- 👤 G David
- 👤 M Duquenne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:38
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
153 words
A device for synchronizing a clock signal with the phase of a received data signal, comprising a local oscillator means for providing a pulsed signal having a frequency equal to a Multiple of the clock signal, a binary frequency divider, means connecting the local oscillator to the binary frequency divider, the frequency divider thereby providing said clock signals, and a phase control signal comprising a digital integrator for integrating the received data signal, transition detecting means for sensing the number zero in the integrator and for providing an indicating pulse each time the integrator passes through the number zero, comparator means for providing a phase difference signal corresponding to the difference in phase between the indicating pulses and the clock signal, the means connecting the local oscillator to the frequency divider comprising a phase correction means for adding and subtracting pulses to the local oscillator signal in response to the phase difference signal.
Claim 2
Independent Claim
153 words
A device for synchronizing a clock signal with the phase of a received data signal, comprising a local oscillator means for providing a pulsed signal having a frequency equal to a Multiple of the clock signal, a binary frequency divider, means connecting the local oscillator to the binary frequency divider, the frequency divider thereby providing said clock signals, and a phase control signal comprising a digital integrator for integrating the received data signal, transition detecting means for sensing the number zero in the integrator and for providing an indicating pulse each time the integrator passes through the number zero, comparator means for providing a phase difference signal corresponding to the difference in phase between the indicating pulses and the clock signal, the means connecting the local oscillator to the frequency divider comprising a phase correction means for adding and subtracting pulses to the local oscillator signal in response to the phase difference signal.
Claim 3
Dependent Claim
192 words
A synchronizing device as claimed in claim 1, characterized in that the transition detection means comprises two up-down counters driven at a frequency equal to half the local oscillator frequency, a data polarity detection circuit, a starting and return-to-zero circuit for the two up-down counters, controlled by the local clock signal, said circuits being arranged to enable the up-down counters to count up or down in dependence upon the polarity of the data, and during a period of time equal to one and a half periods of the local clock signal, the starting instants of one up-down counter being shifted relative to the other over one period of the local clock signal, the two up-down counters being furthermore provided each with three decoding circuits, one for zero, the two others for a threshold of up-count and a threshold of down-count respectively, and a logical assembly controlled by the output signals of the decoding circuits for supplying at the output of the transition detection device, pulses at the zero passages of the up-down counters in response to zero passages preceded by a transgression of either the one or the other of said thresholds.
Claim 4
Dependent Claim
65 words
A synchronizing device as claimed in claim 2 further comprising means for providing a control signal having a frequency equal to half the clock frequency to the logical assembly of the transition detection device for eliminating the pulses produced by the zero passages of the up-down counters during the half period of the local clock signal following the instant of starting of the up-down counter.
Claim 5
Dependent Claim
70 words
A synchronizing device as claimed in claim 1 characterized in that it comprises a device for detecting unstable operation, including a first counter controlled by the indicating pulses, a second counter controlled by a local rhythm corresponding to the transmission rate of the received data signal and a logical circuit inverting the phase of the local clock signal when the first counter steps on less rapidly than the second counter.
Claim 6
Dependent Claim
105 words
A synchronizing device as claimed in claim 1 characterized in that the device for comparing the phase and filtering the transitions comprises a pulse train generator supplying a pulse train at each detected transition, and an up-down counter driven by the output pulses of said generator and controlled to count up or down in dependence upon the polarity of the signals obtained by a shift of the local clock signals equal to half the duration of the pulse train, said up-down counter supplying at two outputs logical signals which control the correction device when attaining either the one or the other of said threshold counts.
Claim 7
Dependent Claim
83 words
A synchronizing device as claimed in claim 1 characterized in that the correction device is formed by a logical circuit controlled by the logical phase-correction signals supplied by the up-down counter of the phase comparison and filtering device comparing the phase and filtering the transitions so that a binary element is added to or subtracted from the signal applied to the binary divider which supplies the local clock signal, said up-down counter being reset to zero when the phase correction is carried out.
Claim 8
Independent Claim
209 words
A device for synchronizing a cloCk signal with the phase and the frequency of a received data signal, comprising a local oscillator means for providing a pulsed signal having a frequency equal to the multiple of the clock signal, a binary frequency divider, means connecting the local oscillator to the frequency divider, the frequency divider thereby providing said clock signals, frequency adjusting means connected to said local oscillator for detecting frequency differences between the clock signal and the received data signals and for providing a control signal to the local oscillator for synchronizing the frequency of the local oscillator with the frequency of the received data signal and a phase control circuit operating independently of the frequency adjusting means and comprising a digital integrator for integrating the received data signals, transition detecting means for sensing the number zero in the integrators and for providing an indicating pulse each time the integrator passes through the number zero, comparator means for providing a phase difference signal corresponding to the difference in phase between the indicating pulses and the clock signal, the means connecting the local oscillator to the frequency divider comprising phase correction means for adding and subtracting pulses to the local oscillator signal in response to the phase difference signal.
Claim 9
Independent Claim
209 words
A device for synchronizing a cloCk signal with the phase and the frequency of a received data signal, comprising a local oscillator means for providing a pulsed signal having a frequency equal to the multiple of the clock signal, a binary frequency divider, means connecting the local oscillator to the frequency divider, the frequency divider thereby providing said clock signals, frequency adjusting means connected to said local oscillator for detecting frequency differences between the clock signal and the received data signals and for providing a control signal to the local oscillator for synchronizing the frequency of the local oscillator with the frequency of the received data signal and a phase control circuit operating independently of the frequency adjusting means and comprising a digital integrator for integrating the received data signals, transition detecting means for sensing the number zero in the integrators and for providing an indicating pulse each time the integrator passes through the number zero, comparator means for providing a phase difference signal corresponding to the difference in phase between the indicating pulses and the clock signal, the means connecting the local oscillator to the frequency divider comprising phase correction means for adding and subtracting pulses to the local oscillator signal in response to the phase difference signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-10 | 1977-06-11 | 1977-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-10 | 1981-06-11 | 1981-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-10 | 1985-06-11 | 1985-12-11 | $7700.00 | Window Closed / Lapsed |