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US3774171A
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Read only memory organization
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1971-11-08
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Granted: 1973-11-20
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Expires: 1991-11-08
Abstract
Abstract A read only memory is provided which minimizes the number of solid state elements required by having these elements represent the fewer number of binary states in each digit line. Inverter means are also provided to ensure a consistent representation to the output of the read only memory plane. A further feature completely eliminates the solid state elements by substituting a plurality of digit lines and solid interconnections for the solid elements previously required. The invention may be utilized in a recognition system having a multisignal address and a plurality of memory planes.
Inventors
- 👤 W Regitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:08
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/06
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
108 words
A read only memory comprising: a plurality of digit lines, each said digit line including a group of sub-digit lines; a plurality of word lines arranged transverse to said sub-digit lines; a plurality of coupling means for electrically coupling said sub-digit lines and said word lines in accordance with information stored in said memory, said information including a first binary state and a second binary state; said coupling means for each said digit line representing that binary state which is the lesser number of binary states of said each said digit line; complementer means coupled to said digit lines having coupling means representing one of said binary states.
Claim 2
Dependent Claim
108 words
A read only memory comprising: a plurality of digit lines, each said digit line including a group of sub-digit lines; a plurality of word lines arranged transverse to said sub-digit lines; a plurality of coupling means for electrically coupling said sub-digit lines and said word lines in accordance with information stored in said memory, said information including a first binary state and a second binary state; said coupling means for each said digit line representing that binary state which is the lesser number of binary states of said each said digit line; complementer means coupled to said digit lines having coupling means representing one of said binary states.
Claim 3
Dependent Claim
21 words
A memory as defined in claim 1 wherein: each said sub-digit line includes no more than one coupling means connected thereto.
Claim 4
Dependent Claim
32 words
A memory as defined in claim 2 wherein: the number of sub-digit lines in said each group of sub-digit lines is not greater than one-half the total number of said word lines.
Claim 5
Dependent Claim
35 words
A memory as defined in claim 3 wherein: the number of sub-digit lines in said each group of sub-digit lines is equal to the number of said coupling means in said group of sub-digit lines.
Claim 6
Dependent Claim
15 words
A memory as defined in claim 4 wherein: said coupling means is a physical interconnection.
Claim 7
Dependent Claim
186 words
A read only memory comprising: a plurality of word lines; a plurality of digit lines arranged in a matrix with said word lines; a plurality of coupling means for connecting some intersection of said matrix, said coupling means representing information in either a first or second binary state; said coupling means representing said first binary state for each of said digit lines wherein the total number of said first binary states is less than the total number of said second binary states; said coupling means along the remainder of said digit lines representing said second binary state; complementer means coupled to said digit lines having said means representing a first binary state; at least a first address selector, said first address selector electrically connected to said word lines to selectively energize one of said word lines; a plurality of first gating means coupled to said plurality of digit lines, said plurality of first gating means includes a plurality of gating elements, each of said plurality of gating elements having a first and second input, a plurality of first output terminals electrically coupled to said digit lines.
Claim 8
Dependent Claim
186 words
A read only memory comprising: a plurality of word lines; a plurality of digit lines arranged in a matrix with said word lines; a plurality of coupling means for connecting some intersection of said matrix, said coupling means representing information in either a first or second binary state; said coupling means representing said first binary state for each of said digit lines wherein the total number of said first binary states is less than the total number of said second binary states; said coupling means along the remainder of said digit lines representing said second binary state; complementer means coupled to said digit lines having said means representing a first binary state; at least a first address selector, said first address selector electrically connected to said word lines to selectively energize one of said word lines; a plurality of first gating means coupled to said plurality of digit lines, said plurality of first gating means includes a plurality of gating elements, each of said plurality of gating elements having a first and second input, a plurality of first output terminals electrically coupled to said digit lines.
Claim 9
Dependent Claim
69 words
A memory as defined in claim 6 further including: a second address selector having a plurality of output lines; said first input to said gating elements electrically connected to one of said output lines of said second address selector; said second input to said gating elements electrically connected to one of said digit lines; and said gating elements having an output coupled to one of said first output terminals.
Claim 10
Dependent Claim
102 words
A memory as defined in claim 7 and further including: a third address selector having a plurality of second output lines; a plurality of second gating means, each having a third and a fourth input and an output; said third input to said second gating means electrically connected to one of said second output lines from said third address selector; said fourth input to said second gating means electrically connected to said one of said first output terminals; said output of said plurality of second gating means connected to a second output terminal; said second output terminal providing a selected binary state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-19 | 1977-05-21 | 1977-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-19 | 1981-05-21 | 1981-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-19 | 1985-05-21 | 1985-11-20 | $7700.00 | Window Closed / Lapsed |