Bilateral switching array with crosspoint storage

Claim 2

In a crosspoint storage device for a switching matrix in a time division switching system comprising first input means, first output means, first and second storage means, means connecting said first input and said first output means to both of said storage means, and first control means for alternately directing, first, the simultaneous reception of information from said first input means by said first storage means and transmission of information to said first output means by said second storage means, and, then, the simultaneous reception of information from said first input means by said second storage means and transmission of information to said first output means by said first storage means, the improvement comprising: A. second input means, B. second output means, C. a system or interconnecting and uniquely associating said first and second input and said first and second output means with both of said storage means comprising 1. means for applying, to said first storage means, signals appearing during selected time slots of a first time division frame on said first input means, 2. means for applying, to said second storage means, signals appearing during consecutive time slots of said first frame on said second input means, 3. means for reading from said first storage means and applying to said first output means during consecutive time slots of a second frame those signals stored in said first storage means during said first frame, and 4. means for reading from said second storage means and applying to said second output means during said selected time slots those signals stored in said second storage means during said first frame, and D. second control means for alternately directing 1. the simultaneous a. rectption of information from said second input means by said second storage means, and b. transmission of information to said second output means by said first storage means, and 2. subsequent to step (1) the simultaneous a. reception of information from said second input means by said first storage means, and b. transmission of information to said second output means by said second storage means.

Claim 3

In a time division multiplex communication system in which data are communicated in alternate even and odd time division multiplex signal frames, each of said frames having a plurality of ordered time slots, a bilateral crosspoint store for coupling first and second time division multiplex input lines to first and second time division multiplex output lines comprising: A. first shared coupling means connected between said input lines and said output lines for receiving signals present in selected one of said time slots of each even signal frame from said first input line, and for transmitting the signals so received to said first output line in successive time slots beginning with an identified time slot of the next following odd signal frame, and for receiving signals present in successive time slots beginning with the starting time slot of each odd signal frame from said second input line, and for transmitting the signal so received to said second output line in selected ones of the time slots of the next following even signal frame, and B. second shared coupling means connected between said input lines and said output lines for receiving signals present in successive time slots beginning with an identified time slot of each odd signal frame from said second input line, and for transmitting the signals so received to said second output line in selected ones of time slots of the next following even signal frame.

Claim 4

In a time division multiplex communication system in which data are communicated in alternate even and odd time division multiplex signal frames, each of said frames having a plurality of ordered time slots, a bilateral crosspoint store for coupling first and second time division multiplex input lines to first and second time division multiplex output lines comprising: A. first shared coupling means connected between said input lines and said output lines for receiving signals present in selected one of said time slots of each even signal frame from said first input line, and for transmitting the signals so received to said first output line in successive time slots beginning with an identified time slot of the next following odd signal frame, and for receiving signals present in successive time slots beginning with the starting time slot of each odd signal frame from said second input line, and for transmitting the signal so received to said second output line in selected ones of the time slots of the next following even signal frame, and B. second shared coupling means connected between said input lines and said output lines for receiving signals present in successive time slots beginning with an identified time slot of each odd signal frame from said second input line, and for transmitting the signals so received to said second output line in selected ones of time slots of the next following even signal frame.

Claim 5

means for applying, to said second storage means, signals appearing during consecutive time slots of said first frame on said second input means,

Claim 6

means for applying, to said second storage means, signals appearing during consecutive time slots of said first frame on said second input means,

Claim 7

subsequent to step (1) the simultaneous a. reception of information from said second input means by said first storage means, and b. transmission of information to said second output means by said second storage means.

Claim 8

subsequent to step (1) the simultaneous a. reception of information from said second input means by said first storage means, and b. transmission of information to said second output means by said second storage means.

Claim 9

first and second memories for storing applied signals,

Claim 10

first and second memories for storing applied signals,

Claim 11

the input line of said designated set of said second group of sets to the output line of said designated set of said first group of sets, and B. unitary control means for selectively enabling crosspoints in said mstrix.

Claim 12

the input line of said designated set of said second group of sets to the output line of said designated set of said first group of sets, and B. unitary control means for selectively enabling crosspoints in said mstrix.

Claim 13

means for applying to said first memory signals appearing during said selected time slots in a first time division frame on said first input line,

Claim 14

means for applying to said first memory signals appearing during said selected time slots in a first time division frame on said first input line,

Claim 15

Apparatus according to claim 2 further comprising a source of control signals designating an identified time slot in eacH of said signal frames and selected time slots in each of said signal frames, the reception and transmission of signals by said first and second means being responsive to said source of control signals.

Claim 16

means for reading from said first storage means and applying to said first output means during consecutive time slots of a second frame those signals stored in said first storage means during said first frame, and

Claim 17

means for reading from said first storage means and applying to said first output means during consecutive time slots of a second frame those signals stored in said first storage means during said first frame, and

Claim 18

means for reading from said second storage means and applying to said second output means during said selected time slots those signals stored in said second storage means during said first frame, and D. second control means for alternately directing

Claim 19

means for reading from said second storage means and applying to said second output means during said selected time slots those signals stored in said second storage means during said first frame, and D. second control means for alternately directing

Claim 20

Apparatus according to claim 3 further comprising means for supplying a control signal designating an identified terminator time slot in each of said signal frames upon the exhaustion of the signals being transmitted to said first output line.

Claim 21

means for applying to said second memory signals appearing during consecutive time slots of said first frame on said second input line,

Claim 22

means for applying to said second memory signals appearing during consecutive time slots of said first frame on said second input line,

Claim 23

means for reading from said first memory and applying to said first output line during consecutive time slots of a second frame those signals stored in said first memory during said first frame, and

Claim 24

means for reading from said first memory and applying to said first output line during consecutive time slots of a second frame those signals stored in said first memory during said first frame, and

Claim 25

A bilateral crosspoint store for providing time slot interchangeable coupling between a first input line and a first output line, and complementary time slot interchangeable coupling between a second input line and a second output line comprising: timing means for establishing a plurality of time slots in alternate even and odd time division multiplex signal frames, a first control line for receiving signals designating selected ones of said time slots in each of said signal frames, a second control line for receiving signals indicating a starting time slot in each of said signal frames, a local control means for storing and transmitting said designating said indicating signals, a first reversible shift register, responsive to signals on said first and second control lines, said first shift register being uniquely associated with and interconnected between said first and second input lines and said first and second output lines for receiving signals present in selected ones of said time slots of each even signal frame, said selected time slots designated by signals on said first control line, from said first input line, and delivering the signals so received to said first output line in successive time slots beginning with the starting time slot of the next following odd signal frame, and receiving signals present in successive time slots beginning with the starting time slot of each odd signal frame from said second input line, and delivering the signals so received to said second output line in selected ones of the time slots of the next following even signal frame, said selected time slots designated by signals on said first control line, and a second reversible shift register, responsive to signals on said first and second control lines, said second shift register being uniquely associated with and interconnected between said first and second input lines and said first and second output lines for receiving signals present in selected ones of said time slots of each odd signal frame, said selected time slots designated by signals on said first control line, from said first input line, and delivering the signals so received to said first output line in successive time slots beginning with the starting time slot of the next following even signal frame, and receiving signals present in successive time slots beginning with the starting time slot of each even signal frame from said second input line, and delivering the signals so received to said second output line in selected ones of the time slots of the next following odd signal frame, said selected time slots designated by signals on said first control line.

Claim 26

A bilateral crosspoint store for providing time slot interchangeable coupling between a first input line and a first output line, and complementary time slot interchangeable coupling between a second input line and a second output line comprising: timing means for establishing a plurality of time slots in alternate even and odd time division multiplex signal frames, a first control line for receiving signals designating selected ones of said time slots in each of said signal frames, a second control line for receiving signals indicating a starting time slot in each of said signal frames, a local control means for storing and transmitting said designating said indicating signals, a first reversible shift register, responsive to signals on said first and second control lines, said first shift register being uniquely associated with and interconnected between said first and second input lines and said first and second output lines for receiving signals present in selected ones of said time slots of each even signal frame, said selected time slots designated by signals on said first control line, from said first input line, and delivering the signals so received to said first output line in successive time slots beginning with the starting time slot of the next following odd signal frame, and receiving signals present in successive time slots beginning with the starting time slot of each odd signal frame from said second input line, and delivering the signals so received to said second output line in selected ones of the time slots of the next following even signal frame, said selected time slots designated by signals on said first control line, and a second reversible shift register, responsive to signals on said first and second control lines, said second shift register being uniquely associated with and interconnected between said first and second input lines and said first and second output lines for receiving signals present in selected ones of said time slots of each odd signal frame, said selected time slots designated by signals on said first control line, from said first input line, and delivering the signals so received to said first output line in successive time slots beginning with the starting time slot of the next following even signal frame, and receiving signals present in successive time slots beginning with the starting time slot of each even signal frame from said second input line, and delivering the signals so received to said second output line in selected ones of the time slots of the next following odd signal frame, said selected time slots designated by signals on said first control line.

Claim 27

The apparatus of claim 5 wherein said first and second reversible shift registers each comprise a plurality of stages and means for advancing signals stored in said stages stage-by-stage to the right and to the left, in alternate frames, said first shift register being adapted to receive signals from said first input line and to transmit signals to said second output line when advancing signals to the right, and to receive signals from said second input line and to transmit signals to said first output line when advancing signals to the left, and said second shift register being adapted to receive signals from said second input line and to transmit signals to said first output line when advancing signals to the right, and to receive signals from said first input line and to transmit signals to said second output line when advancing signals to the left.

Claim 28

means for reading from said second memory and applying to said second output line during said selected time slots those signals stored in said second memory during said first frame.

Claim 29

means for reading from said second memory and applying to said second output line during said selected time slots those signals stored in said second memory during said first frame.

Claim 30

A time division switching array for establishing spatial and temporal paths for binary signals through a matrix of m rows and n columns comprising: m row input lines, where m is greater than 1; m row output lines, each of which is associated with a particular one of said m row input lines; n column input lines, where n is greater than 1; n column output lines, each of which is associated with a particular one of said n column input lines; a plurality of mn crosspoint storage devices, each of which is connected to one of said m row input lines and to the associated one of said m row output lines, and also to one of said n column input lines and to the associated one of said n column output lines, each of said crosspoint storage devices comprising a plurality of bit storage elements; timing means for defining in a repetitive cycle a plurality of time slots for said binary signals; and unitary control means operative in each cycle to selectively direct said crosspoint storage devices to receive and store binary signals from said row and column input lines, to transmit binary signals received during the previous cycle from said row input lines to said column output lines, and to transmit binary signals received during the previous cycle from said column input lines to said row output lines, said plurality of bit storage devices in each of said crosspoint storage devices providing shared storage for binary signals received from both said row and column input lines.

Claim 31

A time division switching array for establishing spatial and temporal paths for binary signals through a matrix of m rows and n columns comprising: m row input lines, where m is greater than 1; m row output lines, each of which is associated with a particular one of said m row input lines; n column input lines, where n is greater than 1; n column output lines, each of which is associated with a particular one of said n column input lines; a plurality of mn crosspoint storage devices, each of which is connected to one of said m row input lines and to the associated one of said m row output lines, and also to one of said n column input lines and to the associated one of said n column output lines, each of said crosspoint storage devices comprising a plurality of bit storage elements; timing means for defining in a repetitive cycle a plurality of time slots for said binary signals; and unitary control means operative in each cycle to selectively direct said crosspoint storage devices to receive and store binary signals from said row and column input lines, to transmit binary signals received during the previous cycle from said row input lines to said column output lines, and to transmit binary signals received during the previous cycle from said column input lines to said row output lines, said plurality of bit storage devices in each of said crosspoint storage devices providing shared storage for binary signals received from both said row and column input lines.

Claim 32

A switching system for interconnecting a plurality of sets of lines in a communication system, wherein each of said sets comprise an input line and an output line, for the simultaneous transfer of information signals between said sets of lines comprising A. a crosspoint matrix for selectively interconnecting said sets of lines in pairs, each crosspoint in said matrix comprising storage means for storing a plurality of said information signals, each of said storage means being permanently connected between one and only one uniquely associated pair of input lines and one and only one uniquely associated pair of output lines, and B. unitary control means for selectively enabling crosspoints in said matrix.

Claim 33

A switching system for interconnecting a plurality of sets of lines in a communication system, wherein each of said sets comprise an input line and an output line, for the simultaneous transfer of information signals between said sets of lines comprising A. a crosspoint matrix for selectively interconnecting said sets of lines in pairs, each crosspoint in said matrix comprising storage means for storing a plurality of said information signals, each of said storage means being permanently connected between one and only one uniquely associated pair of input lines and one and only one uniquely associated pair of output lines, and B. unitary control means for selectively enabling crosspoints in said matrix.

Claim 34

A switching system for interconnecting a plurality of sets of lines in a communication system, for the simultaneous transfer of information signals between said sets of lines each of said sets comprising an input line and an output line, said plurality of sets being divided into first and second groups of sets, said switching system comprising A. a crosspoint matrix for selectively interconnecting said sets of lines in pairs, each crosspoint in said matrix comprising storage means for storing a plurality of said information signals, said storage means being uniquely associated with a pair of input lines and a pair of output lines, said crosspoint matrix further comprising means for selectively providing time-delayable coupling at a crosspoint of

Claim 35

A switching system for interconnecting a plurality of sets of lines in a communication system, for the simultaneous transfer of information signals between said sets of lines each of said sets comprising an input line and an output line, said plurality of sets being divided into first and second groups of sets, said switching system comprising A. a crosspoint matrix for selectively interconnecting said sets of lines in pairs, each crosspoint in said matrix comprising storage means for storing a plurality of said information signals, said storage means being uniquely associated with a pair of input lines and a pair of output lines, said crosspoint matrix further comprising means for selectively providing time-delayable coupling at a crosspoint of

Claim 36

A switching system in accordance with claim 9 wherein said control means comprises A. memory means for storing a sequence of crosspoint location commands, B. means interconnecting said memory means and said crosspoint matrix for providing first control signals to crosspoints selected in accordance with said crosspoint location commands, said selected crosspoints being responsive to said first control signals for receiving information from respective ones of said input lines of said second group of sEts of lines and simultaneously transmitting information to respective ones of said output lines of said second group of sets, C. means interconnecting groups of crosspoints in said matrix for providing second control signals in sequence to crosspoints within each of said groups of crosspoints, said crosspoints in said groups being responsive to said second control signals for receiving information from respective ones of said input lines of said first group of sets of lines and simultaneously transmitting information to respective ones of said output lines of said first group of sets.

Claim 37

In a time slot interchange system A. first and second time division input and first and second time division output lines each capable of carrying time division signals arranged in a sequence of frames, each of said frames comprising an equal plurality of time slots, and B. a crosspoint store system comprising

Claim 38

In a time slot interchange system A. first and second time division input and first and second time division output lines each capable of carrying time division signals arranged in a sequence of frames, each of said frames comprising an equal plurality of time slots, and B. a crosspoint store system comprising