Expanded multi-stage time connection network

Claim 2

A time division multiplex connection system compRising at least a pair of stage networks each including at least one input stage, an intermediate stage and an output stage, each stage being formed of a certain number of time switches each having a certain number of incoming network lines and a certain number of outgoing network lines, time division multiplex connections between the outgoing lines of said input stage and the incoming lines of said intermediate stage and between the outgoing lines of said intermediate stage and the incoming lines of said output stage, each incoming line and each outgoing line comprising several time channels and each time channel comprising several time slots, each time switch of an input stage of one network being connected also to the incoming lines of the intermediate stage of the other network so that any one time channel of any one input switch can be connected to any one time channel of any one output switch in either network.

Claim 3

A time division multiplex connection system as defined in claim 1, wherein each switch is composed of input means receiving said several time channels on said incoming lines, output means applying said several time channels on said outgoing lines and memory means for transferring said time channels from said input means to said output means.

Claim 4

A time division multiplex connection system as defined in claim 2, wherein said memory means includes control means for transferring a given time channel on one input line to a different time channel on an output line of the associated switch.

Claim 5

A time division multiplex connection system as defined in claim 2, wherein each network comprises only three stages, an input stage comprising p input switches with n inputs and m outputs, an intermediate stage comprising two m intermediate switches with p inputs and q outputs, an output stage comprising q output switches with m inputs and n outputs, each input switch receiving n incoming network lines with x time channels and its m outputs being connected in parallel to respective inputs of m intermediate switches in each network, each output switch having n outgoing network lines with x time channels, the m inputs of each output switch being connected to the outputs of the m intermediate switches, the p inputs and q outputs of each intermediate switch being thus respectively connected to the p input switches and the q output switches so that each network thus determined comprises n2 incoming lines and n2 outgoing lines, whereby a connection is possible between any time channel of the n2 outgoing network lines and any time channel of the n2 outgoing network lines, the traffic being provided without blocking or with blocking depending on the number m of switches of the intermediate stage.

Claim 6

A time division multiplex connection system according to claim 4, wherein the intermediate switches comprise the same number of inputs and outputs (p q), the connection system being thus symmetrical.

Claim 7

A time division multiplex connection system according to claim 2, with each network comprising three stages, the input stage comprising n switches with n inputs and (2n - 1) outputs, the intermediate stage comprising 2(2n- 1) switches with n inputs and n outputs and the output stage comprising n switches with (2n- 1) inputs and n outputs, some of said time division multiplex connections existing between the (2n - 1) outputs of each input switch and the inputs of (2n - 1) intermediate switches in each network and other of said time division multiplex connections existing between the (2n - 1) inputs of each output switch and (2n- 1) intermediate switches in each network so as to form a time connection network without blocking having n2 incoming nEtwork lines and n2 network lines.

Claim 8

A time division multiplex connection system according to claim 1, wherein each time switch at least comprises a plurality of input registers equal in number to the number of incoming network lines to the switch, a plurality of output registers equal in number to the outgoing network lines from the switch, each incoming and outgoing network line comprising 32 time channels, a buffer memory operatively associated with the incoming network lines and constituted by as many addressable memory blocks as there are incoming network lines to store data therefrom, each block comprising 32 words of y bits corresponding to 32 time channels, a control memory operatively associated with the outgoing network lines and constituted by as many memory blocks as there are outgoing network lines, each block comprising 32 words of z bits corresponding to the 32 time channels so that the establishment of a connection between a time channel ti of an input register and a time channel of an output register is effected by means in said control memory writing in the work of z control memory bits associated with the time channel tj of the output register allocated to the nth outgoing network line the address of the buffer memory word associated with the time channel ti of the input register allocated to the mth incoming network line, and wherein each intermediate stage switch further includes a second group of input registers equal in number to the number of incoming lines from the input stage of one network and a second group of addressable memory blocks in said buffer memory thereof corresponding to said second group of input registers, said control memory in each intermediate stage switch having a storage facility for an additional binary element per address word serving to switch said address of one of said second group of input registers.

Claim 9

A time division multiplex connection system as defined in claim 1, wherein each time switch comprises a plurality of input regisers equal in number to the number of incoming network lines to the switch, a plurality of output registers equal in number to the outgoing network lines from the switch, a buffer memory including an individual memory portion for each input register having a plurality of time channels equal in number to the time channels provided by each incoming network line, a control memory having an addressable memory block corresponding to each output register, each memory block having a plurality of time channels equal in number to the time channels provided by each outgoing network line, said control memory including means for transferring data in one time channel in said buffer memory to a different time channel of one of said outgoing network lines in accordance with the address of the input register and time channel thereof stored in the memory block corresponding to the required output register and the time channel of the memory block corresponding to the time channel of the outgoing network line to be used, and wherein each intermediate stage switch further includes a second group of input registers equal in number to the number of incoming lines from the input stage of one network and a second group of addressable memory blocks in said buffer memory thereof corresponding to said second group of input registers, said control memory in each intermediate stage switch having a storage facility for an additional binary element per address word serving to switch said address of one of said second group of input registers.