Patent US3772679A successfully refreshed from Google Patents.
US3772679A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Precessing analog trace display
Assignee: Northrop Grumman Innovation Systems LLC
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Filing: 1971-06-30
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Granted: 1973-11-13
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Expires: 1991-06-30
Abstract
Abstract A signal display circuit includes an analog to digital converter, a recirculating memory, a digital to analog converter, and a CRT display means. The memory and the display means are synchronized so that a bright spot representative of the information contained in one location of the memory is produced on the display means for each shifting of information in the memory. New information replaces existing information in the memory at a rate less than the shifting rate of the memory so that the displayed signal appears to move across the viewing screen at a variable speed and with a constant brightness. When no new information is fed into the memory, the display means will continue to show the position of the signal as represented by the data stored in the memory.
Inventors
- 👤 D Scheer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:24
CPC Classifications
G; G09; G09G; G09G1/00; G09G1/06; G09G1/08; G09G1/12; G01; G01R; G01R13/00; G01R13/04; G01R13/06; G01R13/20; G01R13/22; G01R13/32; G09G1/10; H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/56; H03M1/66; H03M1/74; H03M1/78; H03M1/785
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
141 words
A combination comprising an analog signal input terminal, analog to digital converter means having an input circuit connected to said input terminal, and an output circuit, a selectively variable digital delay means having an input circuit and an output circuit, first circuit means connected between the output circuit of said analog to digital converter means and the input circuit of said delay means, a digital to analog converter means having an input circuit and an output circuit, second circuit means connected between the output circuit of said delay means and the input circuit of said digital to analog converter means, and a control means including a selectively operable switching means, said control means being connected to said delay means for selectively determining in accordance with a selected condition of said switching means, a digital signal delay characteristic of said delay means.
Claim 2
Dependent Claim
141 words
A combination comprising an analog signal input terminal, analog to digital converter means having an input circuit connected to said input terminal, and an output circuit, a selectively variable digital delay means having an input circuit and an output circuit, first circuit means connected between the output circuit of said analog to digital converter means and the input circuit of said delay means, a digital to analog converter means having an input circuit and an output circuit, second circuit means connected between the output circuit of said delay means and the input circuit of said digital to analog converter means, and a control means including a selectively operable switching means, said control means being connected to said delay means for selectively determining in accordance with a selected condition of said switching means, a digital signal delay characteristic of said delay means.
Claim 3
Dependent Claim
70 words
A combination as set forth in claim 1 wherein said analog to digital converter means includes means for producing a plurality of digital signals on corresponding output lines from the output circuit of said analog to digital converter means representative of a digital word and said variable digital delay means includes a separate variable delay means for each of the digital signals to concurrently delay said digital signals in parallel.
Claim 4
Dependent Claim
50 words
A combination as set forth in claim 1 wherein said delay means includes recirculating storage means for the digital signals applied thereto from said analog to digital converter means whereby each recirculation of a digital signal is an incremental delay portion of the signal delay characteristic of said delay means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-12 | 1977-05-14 | 1977-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-12 | 1981-05-14 | 1981-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-12 | 1985-05-14 | 1985-11-13 | $7700.00 | Window Closed / Lapsed |