Communication line multiplexing apparatus having a main memory and an input/output memory

Claim 2

Multiplexing apparatus coupled between a data processor and a plurality of communication lines in order to facilitate the transfer therebetween of data in the form of characters containing a plurality of bits, said apparatus including the combination comprising: A. a first memory; B. a second memory; C. means for selectively coupling said plurality of communication lines to said first memory during a first mode of operation; D. means for selectively coupling said first memory to said second memory during a second mode of operation; and E. means for selectively coupling said second memory to said data processor during a third mode of operation.

Claim 3

The combination of claim 1 further comprising: A. first means for indicating the number of bits received for a character from each of said plurality of communication lines; and B. second means for indicating the number of bits transmitted for a character to each of said plurality of communication lines.

Claim 4

The combination of claim 2 further comprising: A. first means for transferring a character from said second memory to said data processor when said first means for indicating indicates that all bits of a character have been received from at least one of said plurality of communication lines, and B. second means for transferring a character from said data processor to said second memory when said second means for indicating indicates that all bits of a charActer have been transmitted from said second memory to at least one of said plurality of communication lines.

Claim 5

The combination of claim 1 wherein said second memory further comprises: A. a first section having locations for a plurality of data words, each of said data words comprising a receive character for transfer to said processor and a transmit character for transfer to one of said communication lines, each of said characters comprising a plurality of bits; and B. a second section having locations for a plurality of control words, each of said control words indicating the number of bits received for said receive character and the number of bits transmitted for said transmit character.

Claim 6

The combination of claim 4 wherein the number of said data words and the number of said control words are each equal to the number of said communication lines.

Claim 7

The combination of claim 5 wherein each of said control words further indicates segments of a bit to be received or transmitted in order to permit sampling of said bit at a predetermined time.

Claim 8

The combination of claim 6 wherein each of said control words further indicates whether the communication line associated with the control word is active or inactive.

Claim 9

The combination of claim 7 further comprising: A. means for addressing one location of said locations in each of said first and second sections of said second memory during said third mode of operation, said one location associated with one of said communication lines; and B. means for addressing another location in said second memory if said one location includes a control word that indicates that said associated communication line is inactive.

Claim 10

The combination of claim 4 further comprising: A. means for addressing a location of said second section of said second memory; B. control word register means; C. means for transferring the control word of said addressed location from said second memory to said control word register means; D. means for transferring a character from said processor to said second memory if said control word indicates that the character previously in the location addressed has been transmitted over the respective communication line; and E. means for transferring a character from said second memory to said processor if each of the bits of the character in the location addressed has been received from the respective communication line.

Claim 11

The combination of claim 9 further comprising: A. means for transferring a bit of a character in said location addressed from said second memory to said first memory during said second mode of operation; B. means for transferring a bit of a character from said first memory to said location addressed in said second memory during said second mode of operation; C. means for updating said control word in said control register means in accordance with the transferring of said bits; and, D. means for restoring said updated control word into said addressed location of said second section.

Claim 12

The combination of claim 10 wherein each of said bits is transferred during a bit interval and wherein said combination further comprises: A. means for transferring a bit of a character to said second memory from said first memory a plurality of times during said bit interval; and B. means for inhibiting further transfer of said bit to said second memory after a time corresponding to substantially the midpoint of said bit interval such that said bit is sampled at substantially its midpoint.

Claim 13

The combination of claim 11 wherein said control word further indicates the number of times said bit has been transferred to said second memory and wherein said means for inhibiting further comprises: A. first means for incrementing said number indicating the number of times said bit has been transferred each time said bit is transferred; B. means for detecting that said number has been incremented a predetermined number of times; C. second means for incrementing said number in said control word, which number indicates the number of bits received, when said means for detecting detects that said number has been incremented a predetermined number of times; and, D. means coupled with said second means for incrementing for causing the next bit received by said second memory to be written in another location in said second memory.

Claim 14

The combination of claim 1 further comprising: A. means for generating an interrupt signal; and B. means responsive to said interrupt signal for inhibiting said second mode and for enabling said first mode.

Claim 15

The combination of claim 13 further comprising means for enabling the transfer of information with each of said communication lines each time said first mode is enabled.

Claim 16

The combination of claim 14 wherein said communication lines operate selectively at different transmission rates and further comprising further means for generating said interrupt signal at a frequency dependent upon each of said different transmission rates.

Claim 17

The combination of claim 14 wherein said first memory comprises a first segment and a second segment each comprising a plurality of locations corresponding in number to the number of said lines, said first segment coupled to receive information from each of said communication lines and coupled to transfer said received information to said second memory, and said second segment coupled to transmit information to each of said communication lines and coupled to receive information from said second memory.

Claim 18

The combination of claim 16 wherein said first memory further comprises a third segment comprising a plurality of locations equal in number to the number of said locations in each of said first and second segments, said locations in said third segment indicating whether or not the corresponding communications lines are ready, and wherein said combination further comprises: A. means for addressing corresponding locations in each of said segments; B. first register means; C. means for loading said first register means with the contents of said addressed corresponding locations; and D. means for transmitting and receiving information between said first register means and the corresponding communication lines which are ready.

Claim 19

The combination of claim 16 further comprising: A. means for addressing a plurality of corresponding locations in each of said first and second segments; B. first register means; C. means for loading said first register means with the contents of said plurality of addressed corresponding locations; and D. means for transmitting and receiving information between said first register means and the corresponding communication lines which are enabled for information transfer.

Claim 20

The combination of claim 18 wherein any one of said communication lines is enabled for information transfer if both said interrupt signal is generated and the transmission rate of said any one of said communication lines corresponds to the frequency of occurrence of said interrupt signal.

Claim 21

Multiplexing apparatus comprising: A. a main memory having a plurality of first locations, each for storing a receive character and a transmit character and a plurality of second locations each for storing a control word; B. an input/output memory having a plurality of third locations each for storing a bit of a receive character and a plurality of fourth locations each for storing a bit of a transmit character; C. a plurality of communication lines, the number of said first, second, third and fourth locations equal to the number of said communication lines; D. a data processor; E. first means for transferring one of said receive characters from said main memory to said processor during a CPU mode of operation; F. second means for transferring one oF said transmit characters from said processor to said main memory during said CPU mode of operation; G. third means for transferring a bit of one of said receive characters from said input/output memory to said main memory during a Scan mode of operation; H. fourth means for transferring a bit of one of said transmit characters from said main memory to said input/output memory during said Scan mode of operation: I. fifth means for transferring a bit of at least one character from said input/output memory to at least one of said communication lines during an I/O mode of operation; and, J. sixth means for transferring a bit of at least one character from at least one of said communication lines to said input/output memory during said I/O mode of operation.

Claim 22

Multiplexing apparatus comprising: A. a main memory having a plurality of first locations, each for storing a receive character and a transmit character and a plurality of second locations each for storing a control word; B. an input/output memory having a plurality of third locations each for storing a bit of a receive character and a plurality of fourth locations each for storing a bit of a transmit character; C. a plurality of communication lines, the number of said first, second, third and fourth locations equal to the number of said communication lines; D. a data processor; E. first means for transferring one of said receive characters from said main memory to said processor during a CPU mode of operation; F. second means for transferring one oF said transmit characters from said processor to said main memory during said CPU mode of operation; G. third means for transferring a bit of one of said receive characters from said input/output memory to said main memory during a Scan mode of operation; H. fourth means for transferring a bit of one of said transmit characters from said main memory to said input/output memory during said Scan mode of operation: I. fifth means for transferring a bit of at least one character from said input/output memory to at least one of said communication lines during an I/O mode of operation; and, J. sixth means for transferring a bit of at least one character from at least one of said communication lines to said input/output memory during said I/O mode of operation.

Claim 23

The apparatus of claim 20 further comprising: A. means for generating an interrupt signal; B. means responsive to said interrupt signal for enabling the operation of said I/O mode; and, C. means responsive to said interrupt signal for disabling the operation of said Scan mode.

Claim 24

The apparatus of claim 20 further comprising: A. means for enabling said CPU mode for transfer of a receive character to said processor if said control word indicates that all of the bits of said receive characters have been received from said input/output memory; and, B. means for enabling said CPU mode for transfer of a transmit character to said main memory if said control word indicates that all of the bits of a previous transmit character associated with the same communication line has been transferred from said main memory to said input/output memory.

Claim 25

The apparatus of claim 20 further comprising: A. means for updating said control word each time a bit is transferred from said main memory to said input/output memory; and, B. means for updating said control word each time a bit is transferred from said input/output memory to said main memory.

Claim 26

The apparatus of claim 20 wherein each of said bits is received from said communications line during a bit interval and wherein the duration of each Scan mode of operation is for a fraction of a bit interval and wherein said third means for transferring comprises: A. means for updating said control word upon the sensing of each fraction of a bit interval; B. means for writing the value of said bit transferred from said input/output memory to said main memory into said main memory once during each fraction of a bit interval; and, C. means for inhibiting said means for writing of said bit transferred to said main memory after said means for updating has updated said control word a number of times equal to approximately one-half the total number of fractions of said bit interval whereby the value of said bit written into said main memory is the value detected at approximately the midpoint of each bit interval.

Claim 27

The apparatus of claim 20 wherein the transmission rates for some of said communication lines are different and further comprising: A. means for generating a plurality of interrupt signals, each of said interrupt signals occurring at a frequency corresponding to one of said transmission rates; B. means for enabling said I/O mode each time any one of said interrupt signals is generated; C. means for addressing each of said third locations and said fourth location each time one of said interrupt signals is generated; and, D. means for transferring bits between each of a plurality of certain ones of said communication lines and each of said corresponding ones of said third and fourth locations during each I/O mode of operation, said certain ones of said communication lines including those lines whose rate corresponds with the frequency of said interrupt signal which enabled said I/O mode.

Claim 28

The apparatus of claim 20 further comprising: A. means for addressing one of said control words; B. means for uPdating said addressed control word in response to said third and fourth means for transferring; and, C. means for restoring said updated control word in the respective second location of said main memory.

Claim 29

The apparatus of claim 20 wherein said control word indicates whether the corresponding communication line is active or inactive, and further comprising means for inhibiting said CPU mode if said control word indicates that said line is inactive.

Claim 30

The apparatus of claim 20 wherein each of said bits is received from said communication lines during a bit interval and wherein the duration of each Scan mode of operation is for a fraction of a bit interval and wherein said third means for transferring comprises: A. means for updating said control word upon the sensing of a fraction of a bit interval; B. means for inhibiting said third means for transferring until said control word has been updated a number of times equal to approximately one-half the total number of fractions of said bit interval; and, C. means for writing the value of said bit transferred to said main memory, when said third means for inhibiting is not enabled, into said main memory whereby the value of said bit written into said main memory is the value detected at approximately the midpoint of said bit interval.