US3766527A
Expired / Lapsed
US
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Program control apparatus
Assignee: Lockheed Martin Corp
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Filing: 1971-10-01
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Granted: 1973-10-16
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Expires: 1991-10-01
Abstract
Abstract Program control apparatus in which current instruction execution and next instruction fetch occur in overlapped time periods during one instruction cycle. The results of a previous instruction execution are employed to set or not set selected ones of a plurality of condition latches in accordance with a current instruction. The current instruction also includes a test code which when combined in a decoding network with the outputs of the latches will produce a selection signal to a next instruction address multiplexer. The multiplexer will respond thereto to selectively couple one of plural instruction address sources to an instruction address buss. The program control apparatus also includes means responsive to a current instruction test code and the outputs of the condition latches to enable or to inhibit the storage of the results of an instruction execution.
Inventors
- 👤 J Briley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:49
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/3836; G06F9/3842; H; H04; H04L; H04L12/00; H04L12/28; H04L12/2803; H04L12/2807
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
161 words
Computer apparatus comprising an addressable memory for storing a plurality of instructions some of which include a test field; instruction cycle timing means for producing a plurality of instruction cycles; first and second address sources; execution means responsive to said timing means for executing a first instruction during each cycle; memory addressing means responsive to said timing means, to the test field of said first instruction and to the status of a condition resulting from an instruction execution during previous cycle to selectively transmit the contents of one of said address sources to the memory to read therefrom a second instruction; calculation means responsive to said timing means for calculating the memory address of a third instruction during each cycle concurrently with the execution and addressing of the first and second instructions respectfully; and loading means for loading the calculated address of said third instruction in the first source during each cycle after its contents have been transmitted to said memory.
Claim 2
Dependent Claim
161 words
Computer apparatus comprising an addressable memory for storing a plurality of instructions some of which include a test field; instruction cycle timing means for producing a plurality of instruction cycles; first and second address sources; execution means responsive to said timing means for executing a first instruction during each cycle; memory addressing means responsive to said timing means, to the test field of said first instruction and to the status of a condition resulting from an instruction execution during previous cycle to selectively transmit the contents of one of said address sources to the memory to read therefrom a second instruction; calculation means responsive to said timing means for calculating the memory address of a third instruction during each cycle concurrently with the execution and addressing of the first and second instructions respectfully; and loading means for loading the calculated address of said third instruction in the first source during each cycle after its contents have been transmitted to said memory.
Claim 3
Dependent Claim
67 words
Computer apparatus as set forth in claim 1 wherein said memory addressing means includes a condition storage means for storing said status of a condition resulting from an instruction execution during a previous cycle; and first test means responsive to the condition storage means and to the test field of the first instruction to selectively transmit the contents of one of said address sources to the memory.
Claim 4
Dependent Claim
42 words
Computer apparatus as set forth in claim 1 wherein said memory addressing means further includes second test means responsive to the condition storage means and to the test field of the first instruction to selectively inhibit the execution of the first inStruction.
Claim 5
Dependent Claim
151 words
Computer apparatus as set forth in claim 3 wherein the second test means produces a bivalued execute enable signal; wherein said instruction execution means includes a plurality of registers, means responsive to the first instruction to generate a set of execution signals during each instruction cycle, an adder and logic network responsive to the execution signal for performing the operation called for by the first instruction upon the contents of selected ones of said registers to produce a set of execution result signals, selected ones of the execution result signals being coupled to said condition storage means; and wherein gating means responds to one value of the execute enable signal and to the instruction cycle timing means during the next succeeding instruction cycle to load said execution result signals into a selected one of said registers and to the other value of the execute enable signal to inhibit the loading thereof.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-15 | 1977-04-16 | 1977-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-15 | 1981-04-16 | 1981-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-15 | 1985-04-16 | 1985-10-16 | $7700.00 | Window Closed / Lapsed |