Data processing system having an improved fetch overlap feature

Claim 2

A data processing system comprising at least two independently operable memory subsystems for storing program instructions and operand, a programmable data processor operative under control of a program instruction directing the data processor operation for processing an operand, and including a first input for receiving an instruction and a second input for simultaneously receiving an operand, means for coupling an instruction from one of said at least two memory subsystems to said instruction input and for simultaneously coupling an operand from another of said at least two memory subsystems to said operand input, and means responsive to an instruction requiring retrieval of an operand for selectively causing one of said at least two memory subsystems to provide an instruction through said coupling means to said instruction input and simultaneously causing another of said at least two memory subsystems to provide an operand through said coupling means to said operand input.

Claim 3

A data processing system comprising at least two independently operable memory subsystems for storing program instructions and operands, a programmable data processor comprising instruction storage means for storing a program instruction directing the data processor operation and operand storage means for storing an operand for processing, means for coupling an instruction from one of said at least two memory subsystems to the instruction storage means and for simultaneously coupling an operand from another of said at least two memory subsystems to said operand storage means, and means responsive to a stored instruction requiring retrieval of an operand for selectively causing one of said at least two memory subsystems to provide an instruction through said coupling means to said instruction storage means and simultaneously causing another of said at least two memory subsystems to provide an operand through said coupling means to said operand storage means.

Claim 4

A data processing system comprising at least two independently operable memory subsystems for storing program instructions and operands, a programmable data processor comprising instruction storage means for storing a program instruction directing the data processor operation and operand storage means for storing an operand for processing, means for coupling an instruction from one of said at least two memory subsystems to the instruction storage means and for simultaneously coupling an operand from another of said at least two memory subsystems to said operand storage means, and means responsive to a stored instruction requiring retrieval of an operand for selectively causing one of said at least two memory subsystems to provide an instruction through said coupling means to said instruction storage means and simultaneously causing another of said at least two memory subsystems to provide an operand through said coupling means to said operand storage means.

Claim 5

A data processing system according to claim 2 wherein the said memory subsystems are addressable and wherein the last named means comprises means for storing an instruction address, means for storing an operand address and means for coupling said instruction and operand addresses to the respective two memory subsystems for which the instruction and operand are to be obtained.

Claim 6

A data processing system according to claim 3 wherein the said instruction address indicates the particular memory subsystem from which the instruction is to be obtained, the coupling means being operative for coupling the instruction from the indicated memory subsystem to the instruction storage means.

Claim 7

A data processor according to claim 2 wherein said instructions indicate a memory subsystem from which an operand is to be obtained, and the coupling means is operative for coupling the operand from the indicated memory subsystem to said operand storage means.

Claim 8

Apparatus for increasing the processing efficiency of an internally programmed data processing system, the apparatus comprising: a memory system comprising a pair of independently accessible addressable memory subsystems for storing instruction words of a proGram and operand words to be processed under programmatic control, the program including instruction words containing an operator field which specifies that an operand word is to be retrieved from the memory system and also containing an operand address field representative of the address of the operand within the memory system; a register for storing information representing a selected memory system address which contains an instruction word from the program sequence, the register being responsive to control signals to change the information it stores to represent a different memory system address storing a subsequent instruction word from the program sequence; means responsive to the stored information representing selected memory system addresses for fetching selected instruction words from the memory system; a register for temporarily storing the fetched instruction words; and means responsive to the operand address field of an instruction word fetched from the memory system for retrieving an operand word from one of the independently accessible memory subsystems at the same time that the means for fetching instruction words is fetching an instruction word from the other independently accessible memory subsystem.

Claim 9

Apparatus for increasing the processing efficiency of an internally programmed data processing system, the apparatus comprising: a memory system comprising a pair of independently accessible addressable memory subsystems for storing instruction words of a proGram and operand words to be processed under programmatic control, the program including instruction words containing an operator field which specifies that an operand word is to be retrieved from the memory system and also containing an operand address field representative of the address of the operand within the memory system; a register for storing information representing a selected memory system address which contains an instruction word from the program sequence, the register being responsive to control signals to change the information it stores to represent a different memory system address storing a subsequent instruction word from the program sequence; means responsive to the stored information representing selected memory system addresses for fetching selected instruction words from the memory system; a register for temporarily storing the fetched instruction words; and means responsive to the operand address field of an instruction word fetched from the memory system for retrieving an operand word from one of the independently accessible memory subsystems at the same time that the means for fetching instruction words is fetching an instruction word from the other independently accessible memory subsystem.

Claim 10

The apparatus as defined by claim 6 in which the means for fetching selected instructions includes a source bus responsive to stored information representing selected memory system addresses, a pair of buses each coupled to one of the memory subsystems, and switching matrix coupling the source bus to the pair of buses for coupling the stored information representing selected memory system addresses to either of the memory subsystems.

Claim 11

The apparatus as defined by claim 7 wherein the information representing a selected memory system address containing an instruction word contains a bit which indicates the memory subsystem that contains the selected instruction word and the switching matrix couples the stored information representing selected memory system addresses to the indicated memory subsystem in response to the bit.

Claim 12

A data processing system comprising: a memory system having a plurality of memory cells for storing instruction words of program sequences and operand words to be processed under programmatic control, the memory cells being distributed between a pair of addressable memory subsystems each having independent access means for enabling words to be written into or read out of the memory cells therein, thereby allowing simultaneous access to both memory subsystems; a data processor coupled to the memory system for processing operand words as specified by instruction words stored in the memory system, the data processor including means for controlling the fetching of instruction words and the retrieval of operand words from the memory system, the means being responsive to a previously fetched instruction from the program sequence for controlling the retrieval of an operand word out of a memory cell within one of the memory subsystems at the same time that the means controls the fetching of another instruction word of the program sequence from a memory cell within the other memory subsystem.

Claim 13

A data processing system comprising: a memory system having a plurality of memory cells for storing instruction words of program sequences and operand words to be processed under programmatic control, the memory cells being distributed between a pair of addressable memory subsystems each having independent access means for enabling words to be written into or read out of the memory cells therein, thereby allowing simultaneous access to both memory subsystems; a data processor coupled to the memory system for processing operand words as specified by instruction words stored in the memory system, the data processor including means for controlling the fetching of instruction words and the retrieval of operand words from the memory system, the means being responsive to a previously fetched instruction from the program sequence for controlling the retrieval of an operand word out of a memory cell within one of the memory subsystems at the same time that the means controls the fetching of another instruction word of the program sequence from a memory cell within the other memory subsystem.

Claim 14

A data processing system according to claim 9 wherein the means for controlling the fetching of instruction words and the retrieval of operand words comprises a first register for storing information representing an address of a memory cell which contains an instruction word, a second register for storing instruction words which have been read out of a memory cell addressed by the first register, a third register for storing information representing an address of a memory cell which contains an operand word, a fourth register for storing operand words which have been read out of a memory cell addressed by the third register and independent access control elements for controlling the exchange of address information and words between the four registers and the memory system.

Claim 15

A data processing system according to claim 10 wherein the means for controlling the fetching of instruction words and the retrieval of operand words comprises in addition a cross point switching matrix for exchanging address information and words between the registers and either memory subsystem.

Claim 16

A data processing system according to claim 11 wherein 11 number of memory cells are distributed to one of the memory subsystems than to the other and the first and third registers store information having different field lengths and wherein the means for controlling the fetching of instruction words and the retrieval of operand words comprises means responsive to the information having the shorter field length for forming an address for the memory subsystem having the larger number of memory cells.

Claim 17

A data processing system according to claim 12 comprising in addition a storage device responsive to predetermined instruction words which order the data processor to effect an operand access to the memory system for indicating that an operand access has been ordered until the operand access has been completed and wherein the means for controlling the fetching of instruction words and the retrieval of operand words responds to said indication to change the information stored in the first register to represent an address of another instruction word from the program sequence.

Claim 18

A data processing system comprising at least two independently operable memory subsystems for storing program instructions and operands, a programmable data processor operative under control of a program instruction directing the data processor operation for processing an operand and including a first input for receiving an instruction and a second input through which operands may be simultaneously transferred and means for coupling an instruction from one of said at least two memory subsystems to said instruction input and for simultaneously coupling an operand between another of said at least two memory subsystems and said operand input.

Claim 19

A data processing system comprising at least two independently operable memory subsystems for storing program instructions and operands, a programmable data processor operative under control of a program instruction directing the data processor operation for processing an operand and including a first input for receiving an instruction and a second input through which operands may be simultaneously transferred and means for coupling an instruction from one of said at least two memory subsystems to said instruction input and for simultaneously coupling an operand between another of said at least two memory subsystems and said operand input.