Counter using insulated gate field effect transistors

Claim 2

An n-scale counter comprising: first memory cells each having first and second input terminals and one output terminal and cascade connected in a number of n2, the output terminal of the first memory cell being connected to the first input terminal of the next subsequent one, the first memory cell taking out as an output signal at the output terminal an input signal to the first input terminal with a delay of a predetermined length of time, when the second input terminal is at a first voltage level, and resetting an output signal at the output terminal, when the second input terminal is at a second voltage level; a second memory cell having one input terminal and one output terminal and interposed between the foremost and rearmost units of said first cascade connected memory cells, said second memory cell taking out as an output signal at the output terminal an input signal to the input terminal with a delay of a predetermined length of time; an inverter circuit connected in series to said second memory cell between the foremost and rearmost units of said first cascade connected memory cells; and means for connecting the junction of said inverter circuit and said second memory cell to the second input terminals of said first memory cells.

Claim 3

The counter according to claim 1 further comprising a buffer means connected between the rearmost unit of said first cascade connected memory cells and the junction of said inverter circuit and said second memory cell.

Claim 4

The counter according to claim 2 wherein said buffer means includes at least two cascade connected inverter means.

Claim 5

The counter according to claim 1z wherein said second memory cell is connected to the rearmost unit of said first memory cells and coupled to the foremost unit of said first memory cells through said inverter circuit.

Claim 6

The counter according to claim 1 wherein said inverter circuit is connected to the rearmost unit of said first memory cells and coupled to the foremost unit of said first memory cells through said second memory cell.

Claim 7

The counter according to claim 1 wherein said first memory cells each include an inverter means having an input and an output terminal and a NOR means having two input terminals and one output terminal, one of said input terminals being connected to the output terminal of said inverter means and the other being connected to the junction of said second memory cell and said inverter circuit.

Claim 8

The counter according to claim 6 further including: first and second power supply terminals across which an operating potential may be applied; and first and second switching means for connecting said inverter means between said first and second power supply terminals; wherein said NOR means includes a second inverter means having an input terminal and an output terminal, said input terminal being connected to the output terminal of said first mentioned inverter means, third and fourth switching means for connecting said second inverter means between said first and second power supply terminals, a fifth switChing means disposed between said third switching means and said second inverter means and having a control electrode, a sixth switching means disposed between the output terminal of said second inverter means and said second power supply terminal and having a control electrode, the control electrodes of said fifth and sixth switching means being jointly connected to the junction of said second memory cells and said inverter circuit; and clock pulse supplying means for enabling said first and second switching means only during a first time interval and enabling said third and fourth switching means only during a second time interval after said first time interval.

Claim 9

The counter according to claim 7 wherein said first mentioned inverter means includes complementary field effect transistor assembly; wherein said first and second switching means consist of field effect transistors of opposite conductivity types and are connected to those of the field effect transistors included in said inverter means which are of the same conductivity type; wherein said second inverter means of said NOR means includes complementary symmetry field effect transistors; wherein said fourth and fifth switching means are field effect transistors of opposite conductivity types and are connected to those of the field effect transistors included in said second inverter means which are of the same conductivity type; and wherein said third and sixth switching means are field effect transistors of the same conductivity type as those of said fifth and fourth switching means respectively.

Claim 10

The counter according to claim 1 wherein said second memory cell includes at least first and second inverter means.

Claim 11

The counter according to claim 9 further including first and second power supply terminals across which an operating potential may be applied; wherein said first and second inverter means are each provided with an input terminal and an output terminal, the input terminal of said second inverter means being connected to the output terminal of said first inverter means; first and second switching means for connecting said first inverter means to said first and second power supply terminals; and third and fourth switching means for connecting said second inverter means to said first and second power supply terminals; and clock pulse supplying means for enabling said first and second switching means only during a first time interval and enabling said third and fourth switching means only during a second time interval after said first time interval.

Claim 12

The counter according to claim 10 wherein said first and second inverter means include complementary field effect transistor assembly; and wherein said first to fourth switching means are field effect transistors connected to those of the field effect transistors included in said first and second inverter means which are of the same conductivity type.

Claim 13

The counter according to claim 1 wherein said first memory cells each include a NAND means having two input terminals and one output terminal, one of said input terminals being connected to the junction of said second memory cell and said inverter circuit; and an inverter means having an output terminal and an input terminal connected to the output terminal of said NAND means.

Claim 14

The counter according to claim 12 further including first and second power supply terminals across which an operating potential may be applied; wherein said NAND means includes a second inverter means having an input terminal and an output terminal, first and second switching means for connecting said second inverter means to said first and second power supply terminals, a third switching means disposed between said second inverter means and said second switching means and having a control electrode, a fourth switching means disposed between the output terminal of said second inverter means and said first power supply terminal and having a control electroDe, the control electrodes of said third and fourth switching means being connected to the junction of said second memory cell and said inverter circuit; wherein said first mentioned inverter means includes an input terminal connected to the output terminal of said second inverter means and an output terminal; fifth and sixth switching means for connecting said first mentioned inverter means to said first and second power supply terminals; and clock pulse supplying means for enabling the first and second switching means only during a first time interval and enabling said fifth and sixth switching means only during a second time interval after said first time interval.

Claim 15

The counter according to claim 13 wherein said first mentioned inverter means and said second inverter means of the NAND means include complementary field effect transistor assembly; wherein said first, third, fifth and sixth switching means are field effect transistors connected to those of the field effect transistors of said first and second inverter means which are of the same conductivity type; wherein said second switching means is a field effect transistor of the same conductivity type as that of said third switching means; and said fourth switching means is a field effect transistor of the same conductivity type as that of said first switching means.

Claim 16

The counter according to claim 6 further including first and second power supply terminals across which an operating potential may be applied; wherein said inverter means are connected between said first and second power supply terminals; wherein said NOR Means includes a second inverter means disposed between said first and second power supply terminals and having an input terminal and an output terminal, and a first switching means disposed between the output terminal of said second inverter means and said second power supply terminal and having a control electrode which is connected to the junction of said second memory cell and said inverter circuit; a second switching means connected to the input terminal of said first mentioned inverter means; a third switching means for connecting the output terminal of said first mentioned inverter means to the input terminal of said second inverter means; and clock pulse supplying means for enabling said second switching means only during a first time interval and enabling said third switching means only during a second time interval after said first time interval.

Claim 17

The counter according to claim 15 wherein said first mentioned and second inverter means and said first, second and third switching means are field effect transistors of the same conductivity type.

Claim 18

The counter according to claim 16 wherein the conductivity type of said field effect transistors is P type.

Claim 19

The counter according to claim 12 further including first and second power supply terminals across which an operating potential may be applied; wherein said NAND means includes a second inverter means having an input terminal and an output terminal, and a first switching means having a control electrode, said second inverter means and first switching means being connected in series between said first and second power supply terminals, a second switching means connected between the control electrode of said first switching means and the junction of said inverter circuit and said first memory cells; a third switching means connected to the input terminal of said second inverter means; a fourth switching means for connecting the input terminal of said first mentioned inverter means to the output terminal of said second inverter means included in said NAND means, said first mentioned inverter means being connected between the first and second power supply terminals; and clock pulse supplying means for enabling said second and third switching means only during a first time interval and enabling said fourth switching means only during a second time interVal after said first time interval.

Claim 20

The counter according to claim 18 wherein said NAND means, inverter means and switching means include field effect transistors of the same conductivity type.

Claim 21

The counter according to claim 19 wherein the conductivity type of the field effect transistors is P type.

Claim 22

The counter according to claim 7 further including a third inverter means disposed between said first and second power supply terminals and having an output terminal and an input terminal connected to the output terminal of said first mentioned inverter means; a fourth inverter means having an output terminal and an input terminal connected to the output terminal of said third switching means, the output terminal of said fourth inverter means being connected to the output terminal of said first mentioned inverter means; seventh and eighth switching means for connecting said fourth inverter means to said first and second power supply terminals; a fifth inverter means disposed between said first and second power supply terminals and having an output terminal and an input terminal connected to the output terminal of said second inverter means included in said NOR means; ninth and tenth switching means for connecting said fifth inverter means to said first aand second power supply terminals; and clock pulse supplying means for enabling said seventh and eighth switching means only until said first and second switching means which were previously enabled are again brought into operation and enabling said ninth and tenth switching means only until said third and fourth switching means which were previously enabled are again brought into operation.

Claim 23

The counter according to claim 6 further including first and second power supply terminals across which an operating potential may be applied; first and second switching means for connecting said inverter means to said first and second power supply terminals; a second inverter means disposed between said first and second power supply terminals and having an output terminal and an input terminal connected to the output terminal of said first mentioned inverter means; a third inverter means having an output terminal and an input terminal connected to the output terminal of said second inverter means; third and fourth switching means for connecting said third inverter means between said first and second power supply terminals; wherein said NOR means includes a fourth inverter means having an output terminal and an input terminal connected to the output terminal of said third inverter means, a fifth switching means for connecting said fourth inverter means to said first power supply terminal, and a sixth switching means for connecting the output terminal of said fourth inverter means to said second power supply terminal, said sixth switching means having a control electrode connected to the junction of said second memory cell and said inverter circuit; a fifth inverter means having an output terminal and an input terminal connected to the output terminal of said second inverter means, the output terminal of said fifth inverter means being connected to the output terminal of said first mentioned inverter means; seventh and eighth switching means for connecting said fifth inverter means to said first and second power supply terminals; a sixth inverter means having an output terminal and an input terminal connected to the output terminal of said fourth inverter means, the output terminal of said sixth inverter means being connected to the output terminal of said third inverter means; ninth and tenth switching means for connecting said sixth inverter means to said first and second power supply terminals; and clock pulse supplying means for enabling said first and second switching means only during a first time interval and enabling said third and fourth switching means only during a second time interval after said first time interval, and enaBling said seventh and eighth switching means only until said first and second switching means which were previously actuated are again brought into operation and enabling said ninth and tenth switching means only until said third and fourth switching means which were previously operated are again enabled.

Claim 24

The counter according to claim 13 further including a third inverter means disposed between said first and second power supply terminals and having an output terminal and an input terminal connected to the output terminal of said second inverter means; a fourth inverter means having an output terminal and an input terminal connected to the output terminal of said third inverter means, the output terminal of said fourth inverter means being connected to the output terminal of said second inverter means; seventh and eighth switching means for connecting said fourth inverter means to said first and second power supply terminals; a fifth inverter means disposed between said first and second power supply terminals and having an output terminal and an input terminal connected to the output terminal of said first mentioned inverter means; a sixth inverter means having an output terminal and an input terminal connected to the output terminal of said fifth inverter means; ninth and tenth switching means for connecting said sixth inverter means to said first and second power supply terminals; and clock pulse supplying means for enabling said seventh and eighth switching means only until said first and second switching means which were previously enabled are again brought into operation, and enabling said ninth and tenth switching means only until said third and fourth switching means which were previously enabled are again enabled.

Claim 25

The counter according to claim 13 further including a third inverter means disposed between the first and second power supply terminals and having an input terminal connected to the output terminal of said second inverter means included in said NAND means and an output terminal connected to the input terminal of said first mentioned inverter means; a fourth inverter means having an input terminal connected to the output terminal of said third inverter means and an output terminal connected to the output terminal of said second inverter means; seventh and eighth switching means for connecting said fourth inverter means to said first and second power supply terminals; a fifth inverter means disposed between said first and second power supply terminals and having an output terminal and an input terminal connected to the output terminal of said first mentioned inverter means; a sixth inverter means having an input terminal connected to the output terminal of said fifth inverter means and output terminal connected to the output terminal of said first mentioned inverter means; ninth and tenth switching means for connecting said sixth inverter means to said first and second power supply terminals; and clock pulse supplying means for enabling said seventh and eighth switching means only until said first and second switching means which were previously enabled are again put into operation and enabling said ninth and tenth switching means only until said third and fourth switching means which were previously enabled are again brought into operation.

Claim 26

The counter according to claim 15 further including a third inverter means disposed between said first and second power supply terminals and having an output terminal and an input terminal connected to the output terminal of said first mentioned inverter means; a fourth switching means for connecting the output terminal of said third inverter means to the input terminal of said first mentioned inverter means, said fourth switching means being enabled in synchronization with said third switching means; a fourth inverter means disposed between said first and second power supply terminals and having an output terminal and an input Terminal connected to the output terminal of said second inverter means included in said NOR means; and a fifth switching means for connecting the output terminal of said fourth inverter means to the input terminal of said second inverter means, said fifth switching means being enabled in synchronization with said second switching means.

Claim 27

The counter according to claim 15 further including a third inverter means disposed between said first and second power supply terminals and connected betweeen said first mentioned inverter means and said second switching means, said third inverter means having an input terminal connected to said second switching means and an output terminal connected to the input terminal of said first mentioned inverter means; a fourth switching means for connecting the output terminal of said first mentioned inverter means to the input terminal of said third inverter means, said fourth switching means being enabled in synchronization with said third switching means; a fourth inverter means connected between said third switching means and said second inverter means included in said NOR means and having an input terminal connected to said third switching means and an output terminal connected to the input terminal of said second inverter means; and a fifth switching means for connecting the output terminal of said second inverter means to the input terminal of said fourth inverter means, said fifth switching means being enabled in synchronization with said second switching means.

Claim 28

The counter according to claim 18 further including a third inverter means disposed between said first and second power supply terminals and having an output terminal and an input terminal connected to the output terminal of said second inverter means; fifth and sixth switching means for connecting the output terminal of said third inverter means to the input terminal of said second inverter means and the control electrode of said first switching means, said fifth and sixth switching means being enabled in synchronization with said fourth switching means; a fourth inverter means disposed between said first and second power supply terminals and having an output terminal and an input terminal connected to the output terminal of said first mentioned inverter means; and a seventh switching means for connecting the output terminal of said fourth inverter means to the input terminal of said first mentioned inverter means, said seventh switching means being enabled in synchronization with said second and third switching means.

Claim 29

The counter according to claim 18 further including a third inverter means disposed between said first and second power supply terminals and provided with an input terminal connected to the output terminal of said second inverter means and an output terminal connected to said fourth switching means; fifth and sixth switching means for connecting the output terminal of said third inverter means to the input terminal of said second inverter means and the control electrode of said first switching means, said fifth and sixth switching means being enabled in synchronization with said fourth switching means; a fourth inverter means disposed between said first and second power supply terminals and having an output and an input terminal connected to the output terminal of said first mentioned inverter means; and a seventh switching means for connecting the output terminal of said fourth inverter means to the input terminal of said first mentioned inverter means, said seventh switching means being enabled in synchronization with said second and third switching means.