US3639740A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ring counter apparatus
Assignee: Collins Radio Co
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Filing: 1970-07-15
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Granted: 1972-02-01
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Expires: 1990-07-15
Abstract
Abstract A plurality of low-speed flip-flops connected to provide highspeed ring-counter-type operation through the use of parallel operating ring counter and shift register stages. The circuit also comprises means for assuring one and only one logic 1 in the device.
Inventors
- 👤 Raymond P Escoffier
- 👤 Milton R Watson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:15
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15093; H03K23/00; H03K23/40; H03K23/50; H03K23/54
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
119 words
Apparatus for providing a sequentially occurring and continuously operating pulse train comprising, in combination: ring counter means comprising N-stages; shift register means comprising N-stages; means for supplying clock signals to said ring counter means and to said shift register means whereby said shift register means is clocked intermediate the clocking of two adjacent stages of said ring counter means; and gating means connected to receive inputs from said clock means and from the output of one of the stages of said ring counter means and connected to a first stage of said shift register means for activating the first stage of said shift register means intermediate the operation of the first and second stages of said ring counter means.
Claim 2
Dependent Claim
119 words
Apparatus for providing a sequentially occurring and continuously operating pulse train comprising, in combination: ring counter means comprising N-stages; shift register means comprising N-stages; means for supplying clock signals to said ring counter means and to said shift register means whereby said shift register means is clocked intermediate the clocking of two adjacent stages of said ring counter means; and gating means connected to receive inputs from said clock means and from the output of one of the stages of said ring counter means and connected to a first stage of said shift register means for activating the first stage of said shift register means intermediate the operation of the first and second stages of said ring counter means.
Claim 3
Dependent Claim
53 words
Apparatus as claimed in claim 1 wherein: said means for providing clock signals provides opposite phase signals to said ring counter means and said shift register means; and said first stage of said shift register means is activated halfway between the operation of said first and second stages of said ring counter means.
Claim 4
Independent Claim
136 words
The method of assuring the occurrence of one and only one ''''odd'''' output from a ring counter capable of having either a ''''normal'''' or ''''odd'''' output from each stage of N-stages thereof comprising the steps of: periodically sampling the outputs of a first portion of the stages and setting the final stage of the ring counter to a ''''normal'''' output each sampling period until all of said first portion of stage outputs provide ''''normal'''' outputs; and sampling the remaining portion of said N-stages of the ring counter when said first portion of stages are all in a ''''normal'''' output condition to set one of the remaining portion of stages in an ''''odd'''' condition and any remaining stages in a ''''normal'''' condition if at the sample time each of the output stages are in a ''''normal'''' condition.
Claim 5
Independent Claim
136 words
The method of assuring the occurrence of one and only one ''''odd'''' output from a ring counter capable of having either a ''''normal'''' or ''''odd'''' output from each stage of N-stages thereof comprising the steps of: periodically sampling the outputs of a first portion of the stages and setting the final stage of the ring counter to a ''''normal'''' output each sampling period until all of said first portion of stage outputs provide ''''normal'''' outputs; and sampling the remaining portion of said N-stages of the ring counter when said first portion of stages are all in a ''''normal'''' output condition to set one of the remaining portion of stages in an ''''odd'''' condition and any remaining stages in a ''''normal'''' condition if at the sample time each of the output stages are in a ''''normal'''' condition.
Claim 6
Dependent Claim
139 words
Apparatus for assuring the occurrence of one and only one ''''odd'''' output from an N-stage ring counter means each stage of which may provide either a ''''normal'''' or ''''odd'''' output and wherein the N-stages are divided into M- and R-stage portions comprising, in combination: first detection means connected to the M-portion stages of said ring counter means for providing an output for periodically resetting a given one of the R-portion stages of said ring counter means to a ''''normal'''' output condition if one or more of said M-portion stages are in an ''''odd'''' condition; and second detection means connected to said R-portion stages and to said first detection means for resetting one of said R-portion stages to an odd condition and any remaining R-portion stages to a normal condition when all of said N-stages are in a normal condition.
Claim 7
Dependent Claim
139 words
Apparatus for assuring the occurrence of one and only one ''''odd'''' output from an N-stage ring counter means each stage of which may provide either a ''''normal'''' or ''''odd'''' output and wherein the N-stages are divided into M- and R-stage portions comprising, in combination: first detection means connected to the M-portion stages of said ring counter means for providing an output for periodically resetting a given one of the R-portion stages of said ring counter means to a ''''normal'''' output condition if one or more of said M-portion stages are in an ''''odd'''' condition; and second detection means connected to said R-portion stages and to said first detection means for resetting one of said R-portion stages to an odd condition and any remaining R-portion stages to a normal condition when all of said N-stages are in a normal condition.
Claim 8
Dependent Claim
13 words
Apparatus as claimed in claim 4 wherein said R-portion comprises one flip-flop stage.
Claim 9
Dependent Claim
65 words
Apparatus as claimed in claim 4 wherein: each of said stages have true and false outputs; and said first detection means comprises NAND-gating means connected to the false outputs of said N-portion stages and said second detection means comprises NOR-gating means connected to receive the false outputs of said R-portion stages of said ring counter means and a false output of said first NAND-gating means.
References Cited (Backward Citations)
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US3217185A
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US3280343A
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US3513329A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-31 | 1975-08-02 | 1976-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-31 | 1979-08-02 | 1980-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-31 | 1983-08-02 | 1984-02-01 | $7700.00 | Window Closed / Lapsed |