Shift register

Claim 2

Shift register comprising a first and a second delay circuit which each comprise a row of storage elements which each have at least a capacitor and a control electrode, means being provided for supplying clock pulses to the control electrodes of the first and second delay circuits, characterized in that at least a number of storage elements of the first delay circuit are each connected through an auxiliary delay circuit to a storage element of the second delay circuit, the auxiliary delay circuit each comprising a row of storage elements which each have at least a capacitor and a control electrode, means being provided for applying to the control electRodes of these storage elements clock pulses such that the shift rate of the auxiliary delay circuit is lower than the shift rate of the first and second delay circuits.

Claim 3

Shift register as claimed in claim 1, characterized is that the shift rates of the first and second delay circuits are equal, whilst the shift rate for the auxiliary delay circuit is smaller than the shift rate of the first and second delay circuits by a factor equal to the number of auxiliary delay circuits.

Claim 4

Shift register as claimed in claim 1, characterized in that each of the storage elements of the auxiliary delay circuits comprises at least one transistor having an input electrode, a control electrode and an output electrode, the control electrodes of the transistors of each first and each last storage element of the auxiliary delay circuits being jointly connected to a first clock pulse conductor, whilst the capacitors of the first and last storage elements of the auxiliary delay circuits each are connected between the output electrode of the associated transistor and a second clock pulse conductor, the capacitors of the remaining storage elements of the auxiliary delay circuits each being connected between the output electrode and the control electrode of the associated transistor, whilst the control electrodes of the transistors of the remaining storage elements of each of the auxiliary delay circuits are divided in two groups, one group being connected to the second clock pulse conductor and the second group being connected to a third clock pulse conductor.

Claim 5

Shift register as claimed in claim 3, characterized in that the transistors are bipolar transistors, the input electrode being the emitter, the control electrode being the base and the output electrode being the collector.

Claim 6

Shift register as claimed in claim 3, characterized in that the transistors are insulated-gate field effect transistors, the input electrode being constituted by the source electrode, the output electrode by the drain electrode and the control electrode by the gate electrode of the transistor.

Claim 7

Shift register as claimed in claim 3, characterized in that each storage element comprises a first and a second field effect transistor and a capacitor, the capacitor being connected between the drain and the gate of the first transistor, whilst the gate of the first transistor is the control electrode of the storage element and the drain of the first transistor is connected to the output of the storage element via the main current path of the second transistor.

Claim 8

Shift register as claimed in claim 6, characterized in that the gates of the second transistors of the storage elements are connected to points of constant potential.

Claim 9

Shift register as claimed in claim 6, characterized in that the gates of the second transistors of the storage elements are connected to the control electrodes of the respective storage elements.

Claim 10

Shift register as claimed in claim 1, characterized in that at least part of it is made in integrated circuit form in a semiconductor body.