Patent US3231044A successfully refreshed from Google Patents.
Patent US3763436A successfully refreshed from Google Patents.
US3763436A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplitude independent time of arrival detector
Assignee: United States Department of the Navy
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Filing: 1971-12-27
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Granted: 1973-10-02
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Expires: 1991-12-27
Abstract
Abstract A circuit for generating an output pulse with a precise time of occurrence relative to the input trigger signal regardless of varying amplitudes of the input trigger signal.
Inventors
- 👤 W Haw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:23
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/13; H03K5/14
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
368 words
A signal time of arrival detector circuit for generating a uniform output pulse with an accurate and precise time of occurrence relative to the input signal regardless of varying amplitudes of the input signal over a wide dynamic range, comprising: a. a circuit input terminal to which the input signal is fed; b. a voltage comparator means; c. delay line means connected between said input terminal and a first input to said voltage comparator, said delay line means delaying the input signal for a fixed time, the time of occurrence of the input being adjustable to occur at a particular time by varying said delay line means; d. an attenuator means having its input connected between said input terminal and a second input to said voltage comparator, said attenuator means attenuating the input signal more than said delay line, said attenuator means comprising a resistor network consisting of a first resistor in series with a parallel combination of resistors forming a voltage divider; e. said input signal being fed through respective blocking capacitors to both said delay line means and said attenuator means to said voltage comparator means; f. voltage means provided for maintaining the second input to said voltage comparator means positive relative to the first input thereto by a small offset voltage during its quiescent condition when there is no input signal to said circuit input terminal whereby the output signal from said voltage comparator means remains at low level; g. the output of said voltage comparator means being at low level when the voltage at said second input thereto is positive relative to said first input thereto, said voltage comparator means switching to high level when the voltage at the second input thereto becomes negative relative to the first input and switching back to its low level when the voltage at the second input returns to a positive polarity with respect to the first input, identical output pulses being generated for each input pulse, said pulses being uniform with accurate and precise time of occurrence relative to the input signal regardless of varying amplitudes of the input signal, wherein accurate information is derived from input trigger pulses whose amplitude varies over a wide dynamic range.
Claim 2
Dependent Claim
368 words
A signal time of arrival detector circuit for generating a uniform output pulse with an accurate and precise time of occurrence relative to the input signal regardless of varying amplitudes of the input signal over a wide dynamic range, comprising: a. a circuit input terminal to which the input signal is fed; b. a voltage comparator means; c. delay line means connected between said input terminal and a first input to said voltage comparator, said delay line means delaying the input signal for a fixed time, the time of occurrence of the input being adjustable to occur at a particular time by varying said delay line means; d. an attenuator means having its input connected between said input terminal and a second input to said voltage comparator, said attenuator means attenuating the input signal more than said delay line, said attenuator means comprising a resistor network consisting of a first resistor in series with a parallel combination of resistors forming a voltage divider; e. said input signal being fed through respective blocking capacitors to both said delay line means and said attenuator means to said voltage comparator means; f. voltage means provided for maintaining the second input to said voltage comparator means positive relative to the first input thereto by a small offset voltage during its quiescent condition when there is no input signal to said circuit input terminal whereby the output signal from said voltage comparator means remains at low level; g. the output of said voltage comparator means being at low level when the voltage at said second input thereto is positive relative to said first input thereto, said voltage comparator means switching to high level when the voltage at the second input thereto becomes negative relative to the first input and switching back to its low level when the voltage at the second input returns to a positive polarity with respect to the first input, identical output pulses being generated for each input pulse, said pulses being uniform with accurate and precise time of occurrence relative to the input signal regardless of varying amplitudes of the input signal, wherein accurate information is derived from input trigger pulses whose amplitude varies over a wide dynamic range.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-01 | 1977-04-02 | 1977-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-01 | 1981-04-02 | 1981-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-01 | 1985-04-02 | 1985-10-02 | $7700.00 | Window Closed / Lapsed |