Patent US3763433A successfully refreshed from Google Patents.
US3763433A
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System and method for differential pulse code modulation of analog signals
Assignee: Iowa State University Research Foundation Inc
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Filing: 1972-01-13
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Granted: 1973-10-02
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Expires: 1992-01-13
Abstract
Abstract A system for differential pulse code modulation includes a delta modulator receiving an input analog signal. The output data stream of the delta modulator is compressed by grouping it into sequential sets of predetermined size, and a binary code word is generated representative of the number of ONES in each set. This binary code word may be transmitted or the quantity of data to be transmitted may be further reduced according to either of two techniques that are disclosed. In one embodiment, the receiver decodes the transmitted data by determining the number of ONES in each original set according to the received binary code word, and then generates a new set at the receiver similar to the original set in that it has the same number of ONES and ZEROS as the original set, but they occur in a pre-assigned order that may be different than the order of the original set. The resulting bit stream is then converted to analog form by a delta demodulator.
Inventors
- 👤 D Nicholas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:22
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/3002
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
303 words
A system for companded differential pulse code modulation of an analog signal comprising: delta modulator means receiving said analog signal and generating a stream of output binary signals, each bit In said stream representative respectively of whether the input analog voltage at a given sampling time is greater than or less than the predicted value of said analog voltage; first circuit means receiving said stream of bits from said delta modulator means for generating signals comprising a count word representative of the number of binary ONE signals in a set of a predetermined number of bits from said delta modulator; second circuit means including look up circuit means communicating with said first circuit means for generating output binary signals comprising a transmission word for each corresponding count word and having a lesser number of bits than its corresponding count word, at least some of said transmission words representing a predetermined nominal count of ONE signals for a predetermined group of different count words as determined by said look-up circuit means; means for transmitting said transmission words to a digital channel in sequence, said second circuit means further generating signals comprising a binary correction word for each transmission word said binary correction word comprising signals representative of the difference between the actual number of ONE counts in each count word and the nominal ONE count of the corresponding transmission word signal transmitted to said digital channel; and third circuit means receiving said correction word from said look-up circuit means for presetting the count of ONES in said first circuit means to a value representative of the difference between the actual count of the previous count word and the nominal count of the associated transmission word prior to generating a subsequent count word whereby a subsequent transmission word is corrected in accordance with said difference.
Claim 2
Independent Claim
303 words
A system for companded differential pulse code modulation of an analog signal comprising: delta modulator means receiving said analog signal and generating a stream of output binary signals, each bit In said stream representative respectively of whether the input analog voltage at a given sampling time is greater than or less than the predicted value of said analog voltage; first circuit means receiving said stream of bits from said delta modulator means for generating signals comprising a count word representative of the number of binary ONE signals in a set of a predetermined number of bits from said delta modulator; second circuit means including look up circuit means communicating with said first circuit means for generating output binary signals comprising a transmission word for each corresponding count word and having a lesser number of bits than its corresponding count word, at least some of said transmission words representing a predetermined nominal count of ONE signals for a predetermined group of different count words as determined by said look-up circuit means; means for transmitting said transmission words to a digital channel in sequence, said second circuit means further generating signals comprising a binary correction word for each transmission word said binary correction word comprising signals representative of the difference between the actual number of ONE counts in each count word and the nominal ONE count of the corresponding transmission word signal transmitted to said digital channel; and third circuit means receiving said correction word from said look-up circuit means for presetting the count of ONES in said first circuit means to a value representative of the difference between the actual count of the previous count word and the nominal count of the associated transmission word prior to generating a subsequent count word whereby a subsequent transmission word is corrected in accordance with said difference.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-01 | 1977-04-02 | 1977-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-01 | 1981-04-02 | 1981-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-01 | 1985-04-02 | 1985-10-02 | $7700.00 | Window Closed / Lapsed |