Differential coder and decoder

Claim 2

A differential pulse code modulation decoder for decoding a signal in binary digital form to an electrical signal comprising: means including a first timing signal source for applying the digital signal to a converter at a first rate which produces said electrical signal in accordance with said digital signal, logic circuit means for sensing when said digital signal contains a predetermined number of the same binary digit sequentially; and means including a second timing signal source and responsive to the occurrence of said sensed predetermined number to supply said digital signal to said converter at a second rate.

Claim 3

A decoder as set forth in claim 1 comprising further logic circuit means for causing said digital signal to be supplied to said converter at said first rate under control of said first timing signal source when the predetermined number of the same binary digit produced sequentially is broken by a binary digit of the other kind.

Claim 4

A decoder as set forth in claim 1 wherein said second timing signal source produces timing signals having a greater rate than the signals produced by said first timing signal source.

Claim 5

A coder for coding an electrical signal into a digital form comprising: means for applying said electrical signal to a converter, a first timing signal source for causing said converter to produce a digital signal at a first rate, said digital signal comprising binary ''''1''s'''' and ''''0''s'''' in accordance with said electrical signal, said coder including circuit means for sensing when said converter produces a predetermined number of the same binary digit sequentially, a second timing signal source, and means responsive to the occurrence of said predetermined number of the same binary digit for causing said converter to produce said digital signal under the control of said second timing signal source.

Claim 6

A coder for coding an electrical signal into a digital form comprising: means for applying said electrical signal to a converter, a first timing signal source for causing said converter to produce a digital signal at a first rate, said digital signal comprising binary ''''1''s'''' and ''''0''s'''' in accordance with said electrical signal, said coder including circuit means for sensing when said converter produces a predetermined number of the same binary digit sequentially, a second timing signal source, and means responsive to the occurrence of said predetermined number of the same binary digit for causing said converter to produce said digital signal under the control of said second timing signal source.

Claim 7

A coder as claimed in claim 4 wherein the timing rate of said second timing signal source is greater than said first rate.

Claim 8

A coder as claimed in claim 4 and further including logic circuit means responsive to a change in the binary digit output of said converter after the sequential occurrence of said predetermined number of the same binary digit for causing said converter tO produce said digital signal under control of said first timing signal source.

Claim 9

A decoder comprising; a first timing signal source producing timing signals at a first rate, gating means receiving a binary digital signal and gating out said binary digital signal at said first rate, logic means connected to receive the digital output of said gating means comprising: a second timing signal source producing timing signals at a second, greater, rate, means to sense when said gating means produces a predetermined number of the same binary digit sequentially and causing said gating means to gate out said digital signal at said second rate when said predetermined number is sensed, and conversion means connected to the output of said gating means to produce an electrical signal proportional to said digital signal produced by said gating means.

Claim 10

A decoder comprising; a first timing signal source producing timing signals at a first rate, gating means receiving a binary digital signal and gating out said binary digital signal at said first rate, logic means connected to receive the digital output of said gating means comprising: a second timing signal source producing timing signals at a second, greater, rate, means to sense when said gating means produces a predetermined number of the same binary digit sequentially and causing said gating means to gate out said digital signal at said second rate when said predetermined number is sensed, and conversion means connected to the output of said gating means to produce an electrical signal proportional to said digital signal produced by said gating means.

Claim 11

A transmission system comprising a coder and a decoder wherein said coder codes a first electrical signal into digital form and comprising: a first timing signal source for producing timing signals at a first rate, means for applying said first electrical signal to a first converter which produces a digital signal at said first rate, said digital signal comprising binary ''''1''s'''' and binary ''''O''s'''' in accordance with said first electrical signal, logic circuit means to sense when said first converter produces a predetermined number of the same binary digit sequentially, a second timing signal source for producing timing signals at a second greater rate, means responsive to the occurrence of said predetermined number of the same binary digit to cause said first converter to produce said digital signal at said second rate, said decoder which decodes the binary digital output of said first converter to a second electrical signal comprising: a third timing signal source for producing timing signals at said first rate, means for receiving said binary digital output at a third rate and supplying it under control of said third timing signal source to a second converter at said first rate which produces said second electrical signal in accordance with said binary digital output, logic circuit means to sense when said binary digit output contains a predetermined number of the same binary digit sequentially, a fourth timing signal source for producing timing signals at said second rate, and means in said decoder responsive to the occurrence of said sensed predetermined number to supply said binary digit to said second converter at said second rate.

Claim 12

A transmission system comprising a coder and a decoder wherein said coder codes a first electrical signal into digital form and comprising: a first timing signal source for producing timing signals at a first rate, means for applying said first electrical signal to a first converter which produces a digital signal at said first rate, said digital signal comprising binary ''''1''s'''' and binary ''''O''s'''' in accordance with said first electrical signal, logic circuit means to sense when said first converter produces a predetermined number of the same binary digit sequentially, a second timing signal source for producing timing signals at a second greater rate, means responsive to the occurrence of said predetermined number of the same binary digit to cause said first converter to produce said digital signal at said second rate, said decoder which decodes the binary digital output of said first converter to a second electrical signal comprising: a third timing signal source for producing timing signals at said first rate, means for receiving said binary digital output at a third rate and supplying it under control of said third timing signal source to a second converter at said first rate which produces said second electrical signal in accordance with said binary digital output, logic circuit means to sense when said binary digit output contains a predetermined number of the same binary digit sequentially, a fourth timing signal source for producing timing signals at said second rate, and means in said decoder responsive to the occurrence of said sensed predetermined number to supply said binary digit to said second converter at said second rate.

Claim 13

A differential coder comprising: a comparator having a single output and a pair of inputs, means to sample the output of said comparator, a quantizer connected to respond to the sampled output of said comparator and producing its output at a first rate, a coder connected to respond to the output of said quantizer, said coder producing a binary signal comprising ''''1''s'''' and ''''O''s,'''' a summing device connected to receive the output produced by said quantizer, means to supply a message waveform and the output from said summing device to the respective inputs to said comparator, means to sense when the coder produces a predetermined number of the same binary digit sequentially, and means responsive to the occurrence of said predetermined number of the same binary digit to cause said quantizer to produce its output at a second rate.

Claim 14

A differential coder comprising: a comparator having a single output and a pair of inputs, means to sample the output of said comparator, a quantizer connected to respond to the sampled output of said comparator and producing its output at a first rate, a coder connected to respond to the output of said quantizer, said coder producing a binary signal comprising ''''1''s'''' and ''''O''s,'''' a summing device connected to receive the output produced by said quantizer, means to supply a message waveform and the output from said summing device to the respective inputs to said comparator, means to sense when the coder produces a predetermined number of the same binary digit sequentially, and means responsive to the occurrence of said predetermined number of the same binary digit to cause said quantizer to produce its output at a second rate.

Claim 15

A differential coder as set forth in claim 9 wherein said second rate is greater than said first rate.

Claim 16

A differential coder as set forth in claim 9 wherein the predetermined number of same binary digit produced sequentially is three.

Claim 17

A differential coder as set forth in claim 9 wherein the binary digit output of said coder is supplied to an elastic store at said first and second rates and gated out of said elastic store at a third rate.

Claim 18

Apparatus as set forth in claim 12 wherein said third rate is greater than said first rate but less than said second rate.

Claim 19

A differential coder as set forth in claim 13 further comprising means connected to said quantizer and coder to monitor the condition of said elastic store and prevent it from overflowing or from depleting.

Claim 20

A differential coder as set forth in claim 14 wherein said monitoring means comprises: a counter capable of counting up and counting down, said counter being counted in one direction at said first rate and in the other direction at said second rate, means connected to said counter to detect when said elastic store is full and inhibiting said counter from continuing to count up, and means connected to said counter to detect when said store is almost depleted and inhibiting said counter from continuing to count down.

Claim 21

A differential coder as set forth in claim 15 wherein said means to detect when said elastic store is almost depleted causes an additional sample of said comparator and causes said counter to be counted up by one.

Claim 22

A transmission system comprising a differential coder and a decoder wherein said differential coder comprises: a comparator having a single output and a pair of inputs, means to sample the output of said comparator, a quantizer connected to receive the output of said comparator and producing an output at a first rate, a coder connected to said quantizer, said coder producing a binary signal responsive to the output of said quantizer, a summing device connected to receive the output of said quantizer, means to supply a message waveform and the output from said summing device to the respective inputs to said comparator, means to sense when said coder produces a predetermined number of the same binary digit sequentially, means responsive to the occurrence of said predetermined number of the same binary digit to cause said quantizer to produce its output and said coder to produce its binary digital output at a second rate, and said decoder comprising: gating means receiving said binary digits from said coder at a third rate and gating out said binary digits at said first rate, logic means connected to receive the digital output of said gating means comprising: means to sense when said gating means produces a predetermined number of the same binary digit sequentially and causing said gating means to gate out said digital signal at said second rate when said predetermined number is sensed, and conversion means connected to the output of said gating means to produce an electrical signal proportional to said digital signal produced by said gating means.

Claim 23

A transmission system comprising a differential coder and a decoder wherein said differential coder comprises: a comparator having a single output and a pair of inputs, means to sample the output of said comparator, a quantizer connected to receive the output of said comparator and producing an output at a first rate, a coder connected to said quantizer, said coder producing a binary signal responsive to the output of said quantizer, a summing device connected to receive the output of said quantizer, means to supply a message waveform and the output from said summing device to the respective inputs to said comparator, means to sense when said coder produces a predetermined number of the same binary digit sequentially, means responsive to the occurrence of said predetermined number of the same binary digit to cause said quantizer to produce its output and said coder to produce its binary digital output at a second rate, and said decoder comprising: gating means receiving said binary digits from said coder at a third rate and gating out said binary digits at said first rate, logic means connected to receive the digital output of said gating means comprising: means to sense when said gating means produces a predetermined number of the same binary digit sequentially and causing said gating means to gate out said digital signal at said second rate when said predetermined number is sensed, and conversion means connected to the output of said gating means to produce an electrical signal proportional to said digital signal produced by said gating means.

Claim 24

A transmission system in accordance with claim 17 wherein the binary digit output of said coder is supplied to a first elastic store in said coder at said first and second rates and gated out of said first elastic store at said third rate, and a second elastic store in said decoder receiving the output of said first elastic store at said third rate and gating out the information in said third rate and gating out the information in said second elastic store at said first rate and at said second gate when said predetermined number of the same binary digit is detected at the output of said gating means.

Claim 25

A transmission system in accordance with claim 18 wherein said third rate is greater than said first rate but less than said second rate.

Claim 26

A transmission system in accordance with claim 18 and further comprising means connected to said coder to monitor the condition of said first and second elastic stores and prevent them from overflowing or from depleting.

Claim 27

A transmission system in accordance with claim 20 wherein said monitoring means comprises: a counter capable of counting up and counting down, said counter being counted in one direction at said first rate and in the other direction at said second rate, means connected to said counter to detect when said elastic store is full and inhibiting said counter from continuing to count up, and means connected to said counter to detect when said store is almost depleted and inhibiting said counter from continuing to count down.

Claim 28

A transmission system in accordance with claim 21 wherein said means to detect when said elastic store is almost depleted causes an additional sample of said comparator and causes said counter to be counted up by one.