Patent US3761739A successfully refreshed from Google Patents.
US3761739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-metastable asynchronous latch
Assignee: International Business Machines Corp
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Filing: 1972-06-23
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Granted: 1973-09-25
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Expires: 1992-06-23
Abstract
Abstract This specification describes an asynchronous latch employing a tunnel diode to prevent the latch from entering what is referred to as a metastable state. The synchronous latch relies on the coincidental occurrence of at least two signals that occur randomly with respect to one another. When one of the pulses is rising while the other is falling the latch being unable to decipher the situation enters a metastable state and produces an output signal that falls halfway between its usual latched and unlatched outputs. The tunnel diode is used to detect an overlap in the transitions of the two signals and to activate the latch to prevent the occurrence of this metastable state.
Inventors
- 👤 D East
- 👤 D Fugere
- 👤 V Householder
- 👤 G Ling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:14
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/313; H03K3/315; H03K19/00; H03K19/02; H03K19/173; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
236 words
In a latch circuit which has an input stage for accepting multiple inputs and providing an output signal when they are in coincidence and also has a reset stage for latching the latch circuit on theeocc occurrence of said output signal and resetting the latch circuit to place it in condition to sense the next set of multiple input signals, apparatus for improving the sensitivity of the latch to detect overlaps in the leading and trailing edges of the muptiple inputs, comprising: a tunnel diode means coupled to the output of the input stage for switching from its low voltage to high voltage state on the occurrence of an output signal from the input stage; current source means coupled to the tunnel diode with level adjustment means to bias the tunnel diode at a high current level to detect the occurrence of the output signal and a low current level to permit the tunnel diode to switch to the low voltage state when the latch is reset; and delay means for coupling the output of the latch to the adjustment means of the constant current source so that the constant current source is adjusted as a function of the output signal whereby the tunnel diode senses small overlaps in the two signals and holds the output of the input stage at the desired level until the circuit is latched at that level by the reset stage.
Claim 2
Dependent Claim
236 words
In a latch circuit which has an input stage for accepting multiple inputs and providing an output signal when they are in coincidence and also has a reset stage for latching the latch circuit on theeocc occurrence of said output signal and resetting the latch circuit to place it in condition to sense the next set of multiple input signals, apparatus for improving the sensitivity of the latch to detect overlaps in the leading and trailing edges of the muptiple inputs, comprising: a tunnel diode means coupled to the output of the input stage for switching from its low voltage to high voltage state on the occurrence of an output signal from the input stage; current source means coupled to the tunnel diode with level adjustment means to bias the tunnel diode at a high current level to detect the occurrence of the output signal and a low current level to permit the tunnel diode to switch to the low voltage state when the latch is reset; and delay means for coupling the output of the latch to the adjustment means of the constant current source so that the constant current source is adjusted as a function of the output signal whereby the tunnel diode senses small overlaps in the two signals and holds the output of the input stage at the desired level until the circuit is latched at that level by the reset stage.
Claim 3
Dependent Claim
64 words
The latch circuit of claim 1 wherein said current source means includes a transistor whose collector is coupled to the tunnel diode to provide the biasing current to the tunnel diode and whose base is coupled to the delay means for the receipt of signals which are a function of the output signal so that said transistor comprises adjustment means of the delay means.
Claim 4
Dependent Claim
39 words
The latch circuit of claim 1 wherein the input and reset stages are AND gates whose outputs are coupled together and connected to one of the inputs of the reset state to provide the latching function for the latch.
Claim 5
Dependent Claim
24 words
The latch circuit of claim 3 wherein the multiple inputs are clock and data inputs and wherein the reset input is the clock input.
Claim 6
Dependent Claim
24 words
The latch circuit of claim 4 wherein the delay means is for delaying the signal to the transistor until after the clock pulse subsides.
References Cited (Backward Citations)
US3290517A
Cited
US3215863A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-24 | 1977-03-26 | 1977-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-24 | 1981-03-26 | 1981-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-24 | 1985-03-26 | 1985-09-25 | $7700.00 | Window Closed / Lapsed |