Asynchronous computer gating device

Claim 1

A COMPUTER GATING DEVICE COMPRISING FIRST AND SECOND TUNNEL DIODES SERIALLY CONNECTED IN THE ORDER NAMED FROM A FIRST JUNCTION TO AN OUTPUT JUNCTION AND FROM SAID OUTPUT JUNCTION TO A SECOND JUNCTION, SAID SECOND JUNCTION BEING MAINTAINED AT A SUBSTANTIALLY FIXED REFERENCE POTENTIAL LEVEL, SAID FIRST AND SECOND TUNNEL DIODES BEING POLED TO ALLOW NORMAL CURRENT FLOW IN A PREDETERMINED DIRECTION THERETHROUGH FROM SAID FIRST TO SAID SECOND JUNCTIONS AND THE PEAK CURRENT OF SAID FIRST TUNNEL DIODE BEING GREATER THAN THE VALLEY CURRENT AND LESS THAN THE PEAK CURRENT OF SAID SECOND TUNNEL DIODE; MEANS INCLUDING A RESISTOR CONNECTED TO SAID FIRST JUNCTION FOR MAINTAINING A POTENTIAL DIFFERENCE ACROSS SAID FIRST AND SECOND TUNNEL DIODES TO EFFECT CURRENT FLOW THERETHROUGH IN SAID PREDETERMINED DIRECTION, SAID POTENTIAL DIFFERENCE BEING OF A MAGNITUDE TO PRECLUDE BOTH SAID FIRST AND SECOND TUNNEL DIODES SIMULTANEOUSLY CONDUCTING IN THE SWITCHED STATE; A BACKWARD DIODE AND A DELAY LINE SERIALLY CONNECTED FROM SAID OUTPUT JUNCTION AND A THIRD JUNCTION; VOLTAGE MEANS CONNECTED TO SAID THIRD JUNCTION FOR NORMALLY MAINTAINING SAID SECOND TUNNEL DIODE IN A SWITCHED STATE, SAID BACKWARD DIODE BEING POLED TO ISOLATE SAID OUTPUT JUNCTION FROM SAID VOLTAGE MEANS DURING PERIODS THAT SAID SECOND TUNNEL DIODE IS IN SAID SWITCHED STATE; AND LOGIC MEANS HAVING A PLURALITY OF INPUT TERMINALS AND AN OUTPUT TERMINAL, SAID OUTPUT TERMINAL BEING CONNECTED TO SAID FIRST JUNCTION FOR CHANGING THE POTENTIAL LEVEL THEREAT IN RESPONSE TO SIGNALS APPEARING AT SAID INPUT TERMINALS THEREBY TO CHANGE THE RESPECTIVE STATES OF SAID FIRST AND SECOND TUNNEL DIODES FOR A PERIOD DETERMINED BY SAID DELAY LINE WHEREBY AN OUTPUT PULSE IS GENERATED AT SAID OUTPUT JUNCTION.