Semiconductor memory using variable threshold transistors

Claim 2

In combination: a matrix array of electrically variable threshold field-effect semiconductor devices formed on a common substrate and arranged in rows and columns, each device of the type having at least two threshold levels, said devices having a control electrode and first and second electrodes defining the ends of a conduction path; a column conductor per column directly connected to the first electrodes of the devices of the column; a row conductor per row directly connected to the second electrodes of the devices of the row; a control line per row directly connected to the control electrodes of the devices of the row; means for applying a first voltage to the column conductors and row conductors and a second voltage to the control lines of selected ones of the devices to set them to a first threshold state, and means for applying said second voltage to the column and row conductors and said first voltage to the control lines of selected ones of the devices to set them to a second threshold state; and means coupled to said row and column conductors and to said control lines for selectively non-destructively sensing the state of selected devices.

Claim 3

The combination as claimed in claim 1, wherein said substrate is an insulator.

Claim 4

The combination as claimed in claim 2, wherein said substrate material is selected from the group consisting of glass and sapphire.

Claim 5

The combination as claimed in claim 1, wherein said second voltage is a reference potential and wherein the potential difference between said first voltage and said second voltage is greater in magnitude than the highest threshold voltage of the devices.

Claim 6

The combination comprising: a matrix array of electrically variable threshold insulated-gate field-effect transistors directly connected to a common substrate arranged in rows and columns, each transistor having a control electrode and first and second electrodes defining the ends of a conduction path and each conduction path being coupled between a row and a column, each transistor being of the type which in response to a voltage of greater than a given reference value applied between the control and first electrodes in a direction to cause conduction exhibits a first threshold level and which in response to a voltage of greater than a given reference value applied between its control and first electrodes in a direction to inhibit conduction exhibits a second threshold level; a plurality of control lines, equal in number to the number of rows, each line connected to the control electrodes of the transistors of a different row; and means for setting the threshold voltage of at least one selected transistor to one of said first and second threshold levels including means fOr applying one of a first and a second potential to the control line of said selected transistor and the other one of said first and second potentials to the row and column connected to said selected transistor, said first and second potentials differing by more than said given reference value.

Claim 7

The combination comprising: a matrix array of electrically variable threshold insulated-gate field-effect transistors directly connected to a common substrate arranged in rows and columns, each transistor having a control electrode and first and second electrodes defining the ends of a conduction path and each conduction path being coupled between a row and a column, each transistor being of the type which in response to a voltage of greater than a given reference value applied between the control and first electrodes in a direction to cause conduction exhibits a first threshold level and which in response to a voltage of greater than a given reference value applied between its control and first electrodes in a direction to inhibit conduction exhibits a second threshold level; a plurality of control lines, equal in number to the number of rows, each line connected to the control electrodes of the transistors of a different row; and means for setting the threshold voltage of at least one selected transistor to one of said first and second threshold levels including means fOr applying one of a first and a second potential to the control line of said selected transistor and the other one of said first and second potentials to the row and column connected to said selected transistor, said first and second potentials differing by more than said given reference value.

Claim 8

The combination as claimed in claim 5, wherein said setting means includes means for applying a common potential to the control electrodes and to at least one of said first and second electrodes of each non-selected transistor for rendering said non-selected transistors nonconducting.

Claim 9

The combination as claimed in claim 6 wherein said setting means includes means for first setting all of said devices to said first threshold level and for then setting selected ones of said devices to said second threshold level.

Claim 10

The combination as claimed in claim 6, wherein said setting means includes means for first applying said first potential to the control lines of selected transistors and said second potential to the rows and columns connected to said selected transistor to establish said first threshold level in the selected transistors; and means for then applying said second potential to the control lines of selected transistors and said first potential to the rows and columns associated with said selected transistors to establish said second threshold level in said selected transistors.

Claim 11

The combination as claimed in claim 8, wherein said second potential is ground potential and said first potential is positive with respect to ground.

Claim 12

The combination as claimed in claim 9, further providing means for selectively applying read voltages between the control line and the row of selected transistors, said read voltages having a value between said second threshold level and said first threshold level; and means coupled to each column for sensing the output of said transistors in response to said read voltages.

Claim 13

The combination comprising: a word-organized memory array of electrically variable threshold insulated-gate field-effect transistors connected to a common substrate arranged in rows and columns, wherein each row stores the digits of a word; each transistor having a control electrode and first and second electrodes defining the ends of a conduction path, said conduction path being coupled between a row and a column, and each transistor being of the type which in response to a forward biasing voltage of greater than a given reference value applied between the control and first electrodes exhibits a high threshold level and which in response to a reverse biasing voltage of greater than a given reference value applied between its control and first electrodes exhibits a low threshold level; a separate control line connected to the control electrodes of the transistors of each row; a unidirectional source of potential having an amplitude greater than said reference value; and means for applying said source of potential between the control line and the rows and columns of selected transistors in a direction to forward bias said control electrode with respect to said first and second electrodes and then applying said source of potential between the control line and the rows and columns of selected transistors in a direction to reverse bias said control electrode with respect to said first and second electrodes.

Claim 14

The combination comprising: a word-organized memory array of electrically variable threshold insulated-gate field-effect transistors connected to a common substrate arranged in rows and columns, wherein each row stores the digits of a word; each transistor having a control electrode and first and second electrodes defining the ends of a conduction path, said conduction path being coupled between a row and a column, and each transistor being of the type which in response to a forward biasing voltage of greater than a given reference value applied between the control and first electrodes exhibits a high threshold level and which in response to a reverse biasing voltage of greater than a given reference value applied between its control and first electrodes exhibits a low threshold level; a separate control line connected to the control electrodes of the transistors of each row; a unidirectional source of potential having an amplitude greater than said reference value; and means for applying said source of potential between the control line and the rows and columns of selected transistors in a direction to forward bias said control electrode with respect to said first and second electrodes and then applying said source of potential between the control line and the rows and columns of selected transistors in a direction to reverse bias said control electrode with respect to said first and second electrodes.