Bidirectional storage crosspoint matrices for mirror image time division switching systems

Claim 2

In a time division multiplex switching matrix crosspoint circuit for controllably coupling signals between a row coordinate circuit and a column coordinate circuit of the matrix, the improvement comprising input register means for receiving signals from at least one of said coordinate circuits in selected time slots of a time division multiplex signal frame, output register means for transmitting signals to at least one of said coordinate circuits in selected time slots of a time division multiplex signal frame, and means for transferring the contents of said input register means to said output register means at only the end of each signal frame.

Claim 3

The crosspoint circuit in accordance with claim 1 in which said row coordinate circuit comprises first bidirectional circuit means, said column coordinate circuit comprises second bidirectional circuit means, means are provided for coupling selectable incoming signals from said first and second bidirectional circuit means to first and second parts of aid input register means, respectively, means are provided for coupling outgoing signals from first and second parts of said output register means to said first and second bidirectional circuit means, respectively, and means are further provided for controlling both of said coupling means to cause said first part of said input register means to be slaved in operating time with said first part of said output register means, and to cause said second part of said input register means to be slaved in operating time with said second part of said output register means.

Claim 4

The crosspoint circuit in accordance with claim 2 in which said parts of said input and output register means are individual shift registers.

Claim 5

The crosspoint circuit in accordance with claim 2 in which said controlling means comprises a plurality of control memories each having one word storage location for each time slot of a frame, a first one of said memories having stored in at least one of its time slot word locations first signals identifying said switching crosspoint circuit, a second one of said memories having stored in at least one of its time slot word locations second signals identifying said switching crosspoint circuit, and means for coupling said first and second signals to actuate said first parts of said incoming signal coupling means and outgoing signal coupling means and to actuate said second parts of said incoming and outgoing signal coupling means, respectively.

Claim 6

In a time division switching system for operating in accordance with time base signals defining a plurality of time slots in a repetitive time cycle, a matrix having time-multiplexed row circuit pairs and column circuit pairs, bilateral crosspoint devices for coupling each of said row circuit pairs to each of said column circuit pairs, means for separately storing signals received from said row circuit pairs and from said column circuit pairs in said crosspoint devices during time slots of a first cycle, and means, operative in a second cycle, for transferring the stored signals from a first plurality of said devices, at different ones of said row circuit pairs, to one of said interconnected column pairs and from a second plurality of said devices, at different ones of said column circuit pairs, to one of said interconnected row circuit pairs.

Claim 7

In a time division switching system for operating in accordance with time base signals defining a plurality of time slots in a repetitive time cycle, a matrix having time-multiplexed row circuit pairs and column circuit pairs, bilateral crosspoint devices for coupling each of said row circuit pairs to each of said column circuit pairs, means for separately storing signals received from said row circuit pairs and from said column circuit pairs in said crosspoint devices during time slots of a first cycle, and means, operative in a second cycle, for transferring the stored signals from a first plurality of said devices, at different ones of said row circuit pairs, to one of said interconnected column pairs and from a second plurality of said devices, at different ones of said column circuit pairs, to one of said interconnected row circuit pairs.

Claim 8

A bidirectional switching matrix comprising a plurality of crosspoint circuits, a first set of matrix coordinate circuits, a second set of matrix coordinate circuits arranged to be selectably coupled to respective first set circuits through corresponding selectable ones of said cross-point circuits, within each of said first and second sets of coordinate circuits the circuits are arranged in pairs with one circuit of each pair comprising an input circuit with respect to matrix crosspoint circuits to which it is connected and the other circuit of each pair comprising an output circuit with respect to the matrix crosspoint circuits to which it is connected, and buffer storage register means in each of said crosspoint circuits for providing bidirectional signal coupling between one of said circuit pairs of said first set and a circuit pair of said second set.

Claim 9

A bidirectional switching matrix comprising a plurality of crosspoint circuits, a first set of matrix coordinate circuits, a second set of matrix coordinate circuits arranged to be selectably coupled to respective first set circuits through corresponding selectable ones of said cross-point circuits, within each of said first and second sets of coordinate circuits the circuits are arranged in pairs with one circuit of each pair comprising an input circuit with respect to matrix crosspoint circuits to which it is connected and the other circuit of each pair comprising an output circuit with respect to the matrix crosspoint circuits to which it is connected, and buffer storage register means in each of said crosspoint circuits for providing bidirectional signal coupling between one of said circuit pairs of said first set and a circuit pair of said second set.

Claim 10

The switching matrix in accordance with claim 6 in which said storage register means comprises input register means connected in each of said crosspoint circuits to receive signals from said input circuits, output register means connected in each of said crosspoint circuits to apply signals to said output circuits, and a separate control memory corresponding to each of said matrix coordinate circuits, each said memory comprising time slot word storage locations for storing control signals corresponding to each time slot of a time division signal frame, circuit means for supplying control signals for storage in said memory, first and second control switch means, means for coupling control memory output by way of said first and second control switch means to said input and output register means, respectively, in the respective crosspoint circuits connected to its corresponding matrix coordinate circuit, said first and second control switch means including means operable for coupling to the respective register means signals from either said word storage locations or said supplying circuit means, means for coupling to an input of the control memory said first control switch means output, and means for operating said control switch means to couple control signals from said memory through said second switch means while coupling control signals from said supplying means through said first switch means to said control memory input for overwriting the contents of said time slot word storage locations.

Claim 11

The matrix in accordance with claim 6 in which said register means in each crosspoint circuit comprises first shift register means for providing signal coupling from an input circuit of said first set pair of circuits to an output circuit of said second set pair of circuits, and second shift register means for providing signal coupling from an input circuit of said second set pair of circuits to an output circuit of said first pair of circuits.

Claim 12

The switching matrix in accordance with claim 8 in which said first shift register means comprises a first input shift register and a first output shift register, said second shift register means comprises a second input shift register and a second output shift register, first means are provided for operating said first input and second output shift registers in the same time slots of recurring time frames, and second means are provided for operating said second input and first output shift registers in the sane time slots of recurring time frames.

Claim 13

The switching matrix in accordance with claim 9 in which there are provided means for transferring signals from said first input shift register to said first output shift register and from said second input shift register to said second output shift register at the end of each of said time frames.

Claim 14

The switching matrix in accordance with claim 9 in which said means for operating said shift registers comprises a separate control memory for each pair of first set coordinate circuits and connected for enabling the coupling of signals in the input circuit of such pair to predetermined selected ones of said first input shift registers at crosspoints connected to such input circuit, means for further coupling the output of each of said control memories to control similarly and simultaneously the application of signals from said second output shift registers to the output circuit of the same first set circuit pair, a separate control memory for each pair of second set coordinate circuits connected for applying signals in the input circuit of such pair to predetermined selected ones of said second input shift registers at crosspoints connected to such input circuit, means for further coupling the output of each of the last-mentioned control memories to control similarly and simultaneously the application of signals from said first output shift registers to the output circuit of the same second set circuit pair, each of said control memories includes one word location for each time slot of a time frame and has stored therein signals identifying respective crosspoint circuits to be connected to corresponding matrix coordinate circuits in such time slots, and means recurrently reading out the contents of said control memories in word-series sequence at the time slot recurrence rate.

Claim 15

A time division multiplex communication system comprising a plurality of bidirectional, storing crosspoint, switching stages each of which includes at least one bidirectional switching matrix, each of said stages having a first set of receiving and output connections and a second set of receiving and output connections, means for coupling said stages in predetermined tandem sequence including a first and a final bidirectional Switching stage, said coupling means including means for connecting said second set receiving and output connections of a stage to said first set output and receiving connections, respectively, of a following stage in each sequence, means for applying a plurality of time division multiplex signals to said first set of receiving connections of said first stage, and means for receiving signals from said first set of output connections of said first stage, and time slot interchanging means for coupling said second set of output connections of said final stage in said sequence to said second set of input connections in the same stage.

Claim 16

A time division multiplex communication system comprising a plurality of bidirectional, storing crosspoint, switching stages each of which includes at least one bidirectional switching matrix, each of said stages having a first set of receiving and output connections and a second set of receiving and output connections, means for coupling said stages in predetermined tandem sequence including a first and a final bidirectional Switching stage, said coupling means including means for connecting said second set receiving and output connections of a stage to said first set output and receiving connections, respectively, of a following stage in each sequence, means for applying a plurality of time division multiplex signals to said first set of receiving connections of said first stage, and means for receiving signals from said first set of output connections of said first stage, and time slot interchanging means for coupling said second set of output connections of said final stage in said sequence to said second set of input connections in the same stage.

Claim 17

A time division multiplex communication system comprising a plurality of bidirectional switching stages each of which includes at least one bidirectional switching matrix, each of said stages having a firset set of receiving and output connections and a second set of receiving and output connections, each of said matrices including controlled signal storage means at matrix crosspoints thereof for providing buffer storage coupling between said first and second sets of receiving and output connections, means for coupling said stages in predetermined tandem sequence including a first and final bidirectional switching stage, means for applying a plurality of time division multiplex signals to said first set of receiving connections of said first stage, means for receiving signals from said first set of output connections of said first stage, and means for coupling said second set of output connections of said final stage in said sequence to said second set of input connections of the same stage.

Claim 18

A time division multiplex communication system comprising a plurality of bidirectional switching stages each of which includes at least one bidirectional switching matrix, each of said stages having a firset set of receiving and output connections and a second set of receiving and output connections, each of said matrices including controlled signal storage means at matrix crosspoints thereof for providing buffer storage coupling between said first and second sets of receiving and output connections, means for coupling said stages in predetermined tandem sequence including a first and final bidirectional switching stage, means for applying a plurality of time division multiplex signals to said first set of receiving connections of said first stage, means for receiving signals from said first set of output connections of said first stage, and means for coupling said second set of output connections of said final stage in said sequence to said second set of input connections of the same stage.

Claim 21

The method in accordance with claim 14 in which said network includes a plurality of crosspoint switching matrices having row and column circuits and wherein respective row control memories and column control memories provide signals for selecting interconnecting crosspoint circuits, and said no-operation codes storing step is accomplished by writing each row control memory in the same time frame that the code is written in the column control memory of a connecting matrix column of a previous stage, if any, and said step of overwriting said equipment numbers into said control memories is accomplished by writing such numbers in control memories of row and column matrix circuits which are to be interconnected in any given matrix in the same time frame.