Patent US1920785A successfully refreshed from Google Patents.
Patent US3754238A successfully refreshed from Google Patents.
US3754238A
Expired / Lapsed
US
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Method and device for transmitting bivalent signals
Assignee: Individual
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Filing: 1970-04-02
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Granted: 1973-08-21
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Expires: 1990-04-02
Abstract
Abstract The invention is concerned with a coding of telegraphic transistions based on the marking of the instant of a transition within the framework of a division of the definite sequence of the signals into sections having a fixed length shorter than the shortest possible duration of a stage without transition. These sections are subdivided into intervals; the order number of an interval where a transition has taken place is transmitted into reflected binary code, which assures a certain number of advantages.
Inventors
- 👤 J Oswald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:22
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/493
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
287 words
A system including a coder portion and a decoder portion for respectively coding and decoding a bi-level incident signal having binary states of variable duration, the shortest time period between transitions from one binary state to another being a specified duration T, said coder portion comprising: means for generating a series of clock pulses at a frequency H; means, responsive to the receipt of said clock pulses, for sampling said incident signal at the frequency of said clock pulses; means, responsive to said sampling means, for comparing the levels of two successive samples of said signal; means, having k binarY stages, k being a positive integer, for counting said clock pulses within a predetermined range in a recurrent manner, said counting starting at a position n, where n is a positive integer, in the course of an interval Theta which is shorter than the shortest duration T during which the level of an incident signal remains constant, such that the pulses employed by said sampling means are spaced by a duration of approximately Theta /2k ; a memory having k binary locations; means, responsive to the absence of the occurrence of a level change in the course of said interval, for storing, in said memory, data representative of a prescribed count identifying said level as well as the absence of a change thereof; and a transfer means for transferring into said memory the contents of said counting means in response to the output of said comparing means produced upon the occurrence of different levels for two successive samples whereby the occurrence of a change in the level of two successive samples of said signal is indexed according to the position of said level change within the interval.
Claim 2
Independent Claim
287 words
A system including a coder portion and a decoder portion for respectively coding and decoding a bi-level incident signal having binary states of variable duration, the shortest time period between transitions from one binary state to another being a specified duration T, said coder portion comprising: means for generating a series of clock pulses at a frequency H; means, responsive to the receipt of said clock pulses, for sampling said incident signal at the frequency of said clock pulses; means, responsive to said sampling means, for comparing the levels of two successive samples of said signal; means, having k binarY stages, k being a positive integer, for counting said clock pulses within a predetermined range in a recurrent manner, said counting starting at a position n, where n is a positive integer, in the course of an interval Theta which is shorter than the shortest duration T during which the level of an incident signal remains constant, such that the pulses employed by said sampling means are spaced by a duration of approximately Theta /2k ; a memory having k binary locations; means, responsive to the absence of the occurrence of a level change in the course of said interval, for storing, in said memory, data representative of a prescribed count identifying said level as well as the absence of a change thereof; and a transfer means for transferring into said memory the contents of said counting means in response to the output of said comparing means produced upon the occurrence of different levels for two successive samples whereby the occurrence of a change in the level of two successive samples of said signal is indexed according to the position of said level change within the interval.
Claim 3
Dependent Claim
90 words
A system including a coder portion and a decoder portion according to claim 1, said coder portion further including means, responsive to said clock pulses, said clock pulses having a frequency H, for converting said clock pulses into a series of pulses which have a frequency H'' and for shifting the contents from the k locations of said memory in parallel form at a uniform spacing of pi Theta /k and converting said contents into a serial form signal in response to said series of pulses having a frequency H''.
Claim 4
Dependent Claim
81 words
A system including a coder portion and a decoder portion according to claim 1, said coder portion further including means for generating three successive pulses during a sub-portion of said intervals Theta between the last sampling pulse of the interval and the first sampling pulse of the next following interval; and means for introducing the first two of said three pulses into said counting means and for resetting said counting means in response to the third pulse of said three pulses.
Claim 5
Dependent Claim
40 words
A system including a coder portion and a decoder portion according to claim 2, said coder portion further including a means coupled between said memory and said shifting means for transcoding natural binary coded signals into reflected binary coded signals.
Claim 6
Dependent Claim
58 words
A system including a coder portion and a decoder portion according to claim 4, said coder portion further including means responsive to said transcoding means for transferring the contents of said memory which have been transcoded into reflected binary code into said converting means once per interval Theta , in response to the resetting of said counting means.
Claim 7
Dependent Claim
69 words
A system including a coder portion and a decoder portion according to claim 5, said coder portion further including a first decoder connected with said counting means and having three outputs, the first one of which is connected to the input of a three stage delay circuit, whose total delay is less than Theta /k, the output of the third stage delivering a pulse for resetting said counting means.
Claim 8
Dependent Claim
108 words
A system including a coder portion and a decoder portion according to claim 6, wherein the first and second stages of said delay circuit are connected to said counter through a logic circuit which receives said clock pulses, whereby the first pulse in an interval causes the counting means to advance from a count of 1 to 2 and subsequent pulses cause said counter to advance from 2 to 1 + n 2k - 3, while the pulses received from the first and second stages of said delay circuit causes said counting means to advance from 2k -3 to 2k -2 and 2k -2 to 2k -1, respectively.
Claim 9
Dependent Claim
47 words
A system including a coder portion and a decoder portion according to claim 7, said coder Portion further including means responsive to a signal generated by one of said comparing means and the two outputs of said first decoder for supplying a transfer signal to said memory.
Claim 10
Dependent Claim
57 words
A system including a coder portion and a decoder portion according to claim 8, wherein said means for supplying a transfer signal includes an exclusive-OR circuit coupled with a logic circuit for preventing a transfer signal from being transmitted to said memory if said exclusive-OR circuit has emitted a transfer signal to said memory during said interval.
Claim 11
Dependent Claim
136 words
A system according to claim 2, including a coder portion and a decoder portion, said decoder portion having means for converting said serial form signal into a bi-level output signal comprising a shift register made up of k-stages for receiving said serial form signal, a receiver clock generating a series of clock signals connected to said shift register for controlling the shifting of said serial form signal into said shift register, a receiver decoder connected to the respective stages of said shift register for detecting when the contents of the stages of said shift register are representative of one of the numbers 2k -1 and 2k - 2 and providing respective signals indicative thereof and further including a receiver transcoder for converting the contents of said shift register from reflected binary code into natural binary code.
Claim 12
Dependent Claim
75 words
A system including a coder portion and a decoder portion according to claim 10, said decoder portion further including a memory and a receiver transfer means connected to said transcoder for storing the outputs thereof, a receiver counter coupled to said receiver clock for counting the clock signals generated thereby and a comparing means for comparing the contents of said counter with the contents of said memory and generating an output signal upon coincidence thereof.
Claim 13
Dependent Claim
74 words
A system including a coder portion and a decoder portion according to claim 11, wherein said comparing means includes k comparators, each having two inputs one of which is connected to a respective stage of said memory and the other to a corresponding stage of said receiver counter, and a AND gate having k inputs connected to the outputs of said comparators and an output flip-flop connected to the output of said AND circuit.
Claim 14
Dependent Claim
78 words
A system including a coder portion and a decoder portion according to claim 12, wherein an output of one stage of said receiver decoder is connected to said flip-flop, whereby said flip-flop will be reset to a 1 condition upon the decoding of the number 2k-1, and another output of another stage of said receiver decoder is coupled to said flip-flop, whereby said flip-flop will be reset to a 0 condition upon the decoding of the number 2k-2.
Claim 15
Dependent Claim
70 words
A system including a coder portion and a decoder portion according to claim 13, said decoder portion further including a synchronizing means having a counter with k stages, which receives pulses at a frequency H'', which is reset to zero by said receiver decoder and is coupled to a zero position decoder for providing a transfer signal to said receiver transfer means and a signal for resetting said receiver counter.
Claim 16
Dependent Claim
51 words
A system including a coder portion and a decoder portion according to claim 14, said decoder portion further including means, responsive to the coincidence of a zero decoding produced by said zero position decoder and a decoding of a sample condition by said receiver decoder for resetting said flip-flop to zero.
Claim 17
Dependent Claim
65 words
A system including a coder portion and a decoder portion according to claim 15 said decoder portion further including a monostable flip-flop, inserted at the output of said zero position decoder, for delivering said transfer signal and the signal for resetting said receiver counter to 1, for at least the length of time required for the remaining signals to be propagated within the decoding means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-20 | 1977-02-19 | 1977-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-20 | 1981-02-19 | 1981-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-20 | 1985-02-19 | 1985-08-21 | $7700.00 | Window Closed / Lapsed |