Patent US3752970A successfully refreshed from Google Patents.
US3752970A
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Digital attenuator
Assignee: AT&T Inc
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Filing: 1971-12-22
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Granted: 1973-08-14
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Expires: 1991-12-22
Abstract
Abstract Attenuation is performed directly on a compressed PCM code by means of a circuit which treats the characteristic bits and the mantissa bits in accordance with an attenuation algorithm. The characteristic bits are applied to a counter circuit whose output is used to produce a first term of the algorithm and the mantissa bits are applied to a shift register whose output is used to generate a second term of the algorithm. The two terms are added together and used to generate the characteristic bits of the attenuated signal.
Inventors
- 👤 M Aaron
- 👤 H Kaneko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:11
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H04B14/048; H03; H03G; H03G3/00; H03G3/002; H03G7/00; H03G7/007; H03H; H03H17/00; H03H17/0054; H03M; H03M7/00; H03M7/30; H03M7/50
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
327 words
A digital attenuator for directly attenuating a nonlinear segmented code wherein the code consists of a first group of m characteristic digits e1e2- -em defining the segment and a second group of n mantissa digits e1e2 - -en defining the position on the segment, an m cell binary counter to which the characteristic digits are applied in parallel, a shift register to which the mantissa digits are applied in parallel, said shift register having n + xi Max + 1 cells where xi Max is the maximum possible change in segment between the unattenuated and attenuated signals, a first AND gate having at least one inverted input, each input being connected to one cell of said binary counter, a source of clock pulses, means for applying clock pulses to said binary counter to cause it to count for a predetermined number of pulses during which count said first AND gate produces a pulse output, delay means for producing from said first AND gate pulse output one or more pulses delayed in time a predetermined amount, means including a second AND gate for applying clock pulses to said shift register to cause it to produce a sequential pulse output, multiplying means for multiplying the output of said shift register by an attenuation factor, adding means for adding together the outputs of said delay means and said multiplying means and feeding the sum back to a sequential input to said shift register, a third AND gate having xi Max inverted inputs connected to said shift register and an enabling input under control of said source of clock pulses, means for inhibiting the counting action of said counter and the shifting action of said shift register comprising an inverted input to said second AND gate and a fourth AND gate connected to said counter, the output of said third AND gate being applied thereto, and means for extracting in parallel the digital information in said counter and said shift register.
Claim 2
Dependent Claim
327 words
A digital attenuator for directly attenuating a nonlinear segmented code wherein the code consists of a first group of m characteristic digits e1e2- -em defining the segment and a second group of n mantissa digits e1e2 - -en defining the position on the segment, an m cell binary counter to which the characteristic digits are applied in parallel, a shift register to which the mantissa digits are applied in parallel, said shift register having n + xi Max + 1 cells where xi Max is the maximum possible change in segment between the unattenuated and attenuated signals, a first AND gate having at least one inverted input, each input being connected to one cell of said binary counter, a source of clock pulses, means for applying clock pulses to said binary counter to cause it to count for a predetermined number of pulses during which count said first AND gate produces a pulse output, delay means for producing from said first AND gate pulse output one or more pulses delayed in time a predetermined amount, means including a second AND gate for applying clock pulses to said shift register to cause it to produce a sequential pulse output, multiplying means for multiplying the output of said shift register by an attenuation factor, adding means for adding together the outputs of said delay means and said multiplying means and feeding the sum back to a sequential input to said shift register, a third AND gate having xi Max inverted inputs connected to said shift register and an enabling input under control of said source of clock pulses, means for inhibiting the counting action of said counter and the shifting action of said shift register comprising an inverted input to said second AND gate and a fourth AND gate connected to said counter, the output of said third AND gate being applied thereto, and means for extracting in parallel the digital information in said counter and said shift register.
Claim 3
Dependent Claim
164 words
A digital attenuator as claimed in claim 1 wherein said delay means comprises a first delay circuit for delaying the said first AND gate output pulse K clock intervals where K is the number of clock intervals involved in the multiplication process, a second delay circuit for delaying the said first AND gate output pulse K+n+1 intervals, the outputs of said first and second delay circuits being applied to the inputs of a first OR gate, a second OR gate, means for applying the said first AND gate output pulse directly to one input of said second OR gate, a third delay circuit for delaying the said first AND gate output pulse n+1 intervals, the output of said third delay circuit being applied to an input of said second OR gate, multiplying means for multiplying the output of said second OR gate by a multiplication factor, and means for subtracting the output of said multiplying means from the output of said first OR gate.
Claim 4
Dependent Claim
105 words
A digital attenuator as claimed in claim 1 wherein said delay means includes said first AND gate and a fifth AND gate, said first AND gate having three inverted inputs, each connected to a separate cell of said counter, and an enabling input connected to said source of clock pulses, said fifth AND gate having a single inverted input and two enabling inputs, each connected to a separate cell of said counter, and an OR gate having its inputs connected to the outputs of said first and fifth AND gates, the output of the OR gate being connected to one input of said adding means.
Claim 5
Dependent Claim
31 words
A digital attenuator as claimed in claim 1 wherein a pulse generator is connected in series between said source of clock pulses and the enabling input of said third AND gate.
Claim 6
Dependent Claim
286 words
A digital attenuator for directly attenuating a nonlinear segmented signal code wherein the code consists of a first group of m characteristic digits e1e2- -em defining the segment L and a second group of n mantissa digits e1e2- -en defining the quantizing step V in the segment, said attenuator comprising a source of clock pulses t and means for performing on the unattenuated signal L1V, under control of the clock pulses, the algorithm zK 1 W(z'') z S(z) where z is an operator representing multiplication by two and one clock interval delay, K is the number of clock intervals delay in the multiplication process, xi L1-L2 where L1 is the segment term of the unattenuated signal and L2 is the segment term of the attenuated segment code, W(z) represents the attenuated signal, and S(z) is given by A(z) (zV1(z) +zn 1 +1) + z L (1+zn 1) (zK-A(z) ) where A(z) is the transfer function of the attenuation factor, and V1(z) is the mantissa term of the unattenuated signal, said means for performing the algorithm comprising a binary counter and delay network for generating the term z L (1+zn 1) (zK-A(z)), a shift register and multiplier for generating the term A(z) (zV1(z) + zn 1 +1), adder means for combining the two terms to produce S(z), means for applying S(z) to a serial input of the shift register, and means for monitoring the input to the shift register to produce a signal to stop the binary counter when L2 is stored therein and to stop the shift register when V2 is stored therein, where V2 is the mantissa of the attenuated signal, and means for extracting the attenuated signal L2V2 from the counter and shift register.
Claim 7
Dependent Claim
286 words
A digital attenuator for directly attenuating a nonlinear segmented signal code wherein the code consists of a first group of m characteristic digits e1e2- -em defining the segment L and a second group of n mantissa digits e1e2- -en defining the quantizing step V in the segment, said attenuator comprising a source of clock pulses t and means for performing on the unattenuated signal L1V, under control of the clock pulses, the algorithm zK 1 W(z'') z S(z) where z is an operator representing multiplication by two and one clock interval delay, K is the number of clock intervals delay in the multiplication process, xi L1-L2 where L1 is the segment term of the unattenuated signal and L2 is the segment term of the attenuated segment code, W(z) represents the attenuated signal, and S(z) is given by A(z) (zV1(z) +zn 1 +1) + z L (1+zn 1) (zK-A(z) ) where A(z) is the transfer function of the attenuation factor, and V1(z) is the mantissa term of the unattenuated signal, said means for performing the algorithm comprising a binary counter and delay network for generating the term z L (1+zn 1) (zK-A(z)), a shift register and multiplier for generating the term A(z) (zV1(z) + zn 1 +1), adder means for combining the two terms to produce S(z), means for applying S(z) to a serial input of the shift register, and means for monitoring the input to the shift register to produce a signal to stop the binary counter when L2 is stored therein and to stop the shift register when V2 is stored therein, where V2 is the mantissa of the attenuated signal, and means for extracting the attenuated signal L2V2 from the counter and shift register.
Claim 8
Dependent Claim
85 words
A digital attenuator as claimed in claim 5 wherein the means for monitoring comprises a first AND gate having xi Max inverted inputs, where xi Max is the maximum possible change in segment between the unattenuated and attenuated signals, and an enabling input, and means for enabling said first AND gate for a time period from tK n 1 to tK n 1 comprising a pulse generator connected in series between said source of clock pulses and the enabling input of said first AND gate.
Claim 9
Dependent Claim
46 words
A digital attenuator as claimed in claim 6 wherein said shift register has n + xi Max +1 cells and the serial input and the first two of said shift register cells are each connected to one of the inverted inputs of said first AND gate.
Claim 10
Dependent Claim
56 words
A digital attenuator as claimed in claim 7 and further including a second AND gate having an input connected to said sOurce of clock pulses and an inverted input connected to the output of said first AND gate, the output of said second AND gate being connected to said shift register to control the shifting thereof.
Claim 11
Dependent Claim
77 words
A digital attenuator as claimed in claim 8 and further including means for causing said binary counter to count down when there is an output from said first AND gate comprising a third AND gate having one input connected to said source of clock pulses and its other input connected to the output of said first AND gate, the output of said third AND gate being connected to said binary counter to cause it to count down.
Claim 12
Dependent Claim
77 words
A digital attenuator as claimed in claim 8 and further including means for causing said binary counter to stop counting, said means comprising a third AND gate having one input connected to said source of clock pulses and an inverted input connected to the output of said first AND gate, the output of said third AND gate being connected to said counter whereby said counter causes counting when there is an output from said first AND gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-13 | 1977-02-12 | 1977-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-13 | 1981-02-12 | 1981-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-13 | 1985-02-12 | 1985-08-14 | $7700.00 | Window Closed / Lapsed |