Patent US2459239A successfully refreshed from Google Patents.
Patent US5203774A successfully refreshed from Google Patents.
Patent US3751648A successfully refreshed from Google Patents.
US3751648A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Generalized shift register pulse sequence generator
Assignee: Comsat Corp
•
Filing: 1971-12-01
•
Granted: 1973-08-07
•
Expires: 1991-12-01
Abstract
Abstract A generalized pulse sequence generator comprises a plurality of shift register generators, each providing a pulse sequence output. In order to produce one pulse in the sequence the states of the corresponding stages of each shift register generator are modulo-2 multiplied and the resultant outputs from the final multiplier are summed. The shift register generators are clocked at different rates to cause certain ones to run through a complete sequence of register states while others remain at one of their register states. The output sequence comprises a combination of binary pulses, each of which is a result of one multiplication/summation operation and has a period n which is equal to the product of the periods of the individual shift register generators.
Inventors
- 👤 W Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:07
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
109 words
A pulse sequence generator comprising, a. a plurality of shift register sequence generators, each capable of providing a pulse sequence, b. multiplication means for multiplying modulo-2, the states of corresponding stages in said plurality of shift register generators, c. means for adding, modulo-2, all products formed by said multiplication means, the sum formed during each static state of all said shift registers being a single output of said sequence generator, and d. means for variably clocking said shift register generators at relative clock rates to cause any given generator to be clocked n times faster than a preceding generator, where n is the sequence period of said given generator.
Claim 2
Dependent Claim
109 words
A pulse sequence generator comprising, a. a plurality of shift register sequence generators, each capable of providing a pulse sequence, b. multiplication means for multiplying modulo-2, the states of corresponding stages in said plurality of shift register generators, c. means for adding, modulo-2, all products formed by said multiplication means, the sum formed during each static state of all said shift registers being a single output of said sequence generator, and d. means for variably clocking said shift register generators at relative clock rates to cause any given generator to be clocked n times faster than a preceding generator, where n is the sequence period of said given generator.
Claim 3
Dependent Claim
20 words
A pulse sequence generator as claimed in claim 1 wherein said shift register sequence generators are feedback shift register generators.
Claim 4
Dependent Claim
22 words
A pulse sequence generator as claimed in claim 1 wherein said shift register generators are maximal length linear feedback shift register generators.
Claim 5
Dependent Claim
110 words
A pulse sequence generator having a cyclic period equal to n1 X n2, where n1 and n2 are integers and may be equal or unequal, comprising, a. first shift register generator having a cyclic period n1, b. a second shift register generator having a cyclic period n2, c. multiplication means for multiplying the states of corresponding stages of said first and second shift registers modulo-2, d. addition means fo summing modulo-2 the outputs of said multiplication means, and e. clocking means for clocking said first and second shift register generators at relative rates, said second generator being clocked at a rate n2 time the clock rate of said first generator.
Claim 6
Dependent Claim
110 words
A pulse sequence generator having a cyclic period equal to n1 X n2, where n1 and n2 are integers and may be equal or unequal, comprising, a. first shift register generator having a cyclic period n1, b. a second shift register generator having a cyclic period n2, c. multiplication means for multiplying the states of corresponding stages of said first and second shift registers modulo-2, d. addition means fo summing modulo-2 the outputs of said multiplication means, and e. clocking means for clocking said first and second shift register generators at relative rates, said second generator being clocked at a rate n2 time the clock rate of said first generator.
Claim 7
Dependent Claim
24 words
A pulse sequence generator as claimed in claim 4 wherein said first and second shift register generators are maximal length linear shift register generatOrs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-06 | 1977-02-05 | 1977-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-06 | 1981-02-05 | 1981-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-06 | 1985-02-05 | 1985-08-07 | $7700.00 | Window Closed / Lapsed |