Patent US3748652A successfully refreshed from Google Patents.
US3748652A
Expired / Lapsed
US
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Display buffer
Assignee: Northrop Grumman Guidance and Electronics Co Inc
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Filing: 1972-04-10
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Granted: 1973-07-24
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Expires: 1992-04-10
Abstract
Abstract A display buffer is provided with a cyclic memory. Means is provided for writing data into the memory in successive regions and means is provided for reading data out in sequence. Counter means is provided to count the number of messages written into memory and the number of messages read out of memory, and inhibit means is provided to inhibit the write means if the memory becomes fully loaded. The read-out rate may be significantly different from the write-in rate so that the display buffer can accept data messages at a rate equal to computer assimilation and can display messages at a rate compatable to display rate generation.
Inventors
- 👤 R Ward
- 👤 P Yows
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:50
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F5/12; G06F5/14; G06F3/00; G06F3/14; G06F3/153
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
147 words
In a cyclic display memory having a plurality of data storage regions and write means for writing data into successive regions in sequence and read means for extracting data from said regions in sequence, the improvement comprising: first counter means for counting in sequence the number of data messages written into said memory by said write means; second counter means for counting in sequence the number of data messages extracted from said memory by said read means; and gate means responsive to signals from said first and second counter means to provide an inhibit signal when the counts provided by said first and second counter means indicate a condition in said memory that data messages are stored in all regions of said memory which have not been extracted by said read means; and inhibit means responsive to said inhibit signal for inhibiting operation of said write means.
Claim 2
Dependent Claim
147 words
In a cyclic display memory having a plurality of data storage regions and write means for writing data into successive regions in sequence and read means for extracting data from said regions in sequence, the improvement comprising: first counter means for counting in sequence the number of data messages written into said memory by said write means; second counter means for counting in sequence the number of data messages extracted from said memory by said read means; and gate means responsive to signals from said first and second counter means to provide an inhibit signal when the counts provided by said first and second counter means indicate a condition in said memory that data messages are stored in all regions of said memory which have not been extracted by said read means; and inhibit means responsive to said inhibit signal for inhibiting operation of said write means.
Claim 3
Dependent Claim
40 words
Apparatus according to claim 1 wherein said memory is connected to a central computer, and further including means responsive to said inhibit means for transmitting a message to said central computer indicative of a fully loaded condition in said memory.
Claim 4
Dependent Claim
52 words
Apparatus according to claim 2 wherein said memory has n regions addressed sequentially and cyclically, each of said first and second counters cyclically counting to n, said gate means being operable to provide said inhibit signal when the count in said first counter means equals the count in said second counter means.
Claim 5
Dependent Claim
52 words
Apparatus according to claim 1 wherein said memory has n regions addressed sequentially and cyclically, each of said first and second counters cyclically counting to n, said gate means being operable to provide said inhibit signal when the count in said first counter means equals the count in said second counter means.
Claim 6
Dependent Claim
208 words
A statistical display buffer comprising, in combination: selection means adapted to be connected to a central computer to receive data messages from said central computer, said data messages having a select code unique to an individual selection means, said selection means being responsive to the select code of each such data message to pass data messages associated with the select code of the said selection means; cyclic data storage means for storing data messages; write means for storing data messages passed by said selection means at a first rate; write counter means connected to said write means for counting the number of data messages stored in said storage means; read-out means connected to said storage means for extracting data messages from said storage means at a second rate independent of said first rate; read counter means connected to said read-out means for counting the number of data messages extracted from said storage means; and inhibit means responsive to the counts in said write and read counter means for inhibiting operation of said write means when the counts of said write and read counter means indicate that said storage means contains data messages in all regions of said storage means which have not been extracted by said read-out means.
Claim 7
Dependent Claim
208 words
A statistical display buffer comprising, in combination: selection means adapted to be connected to a central computer to receive data messages from said central computer, said data messages having a select code unique to an individual selection means, said selection means being responsive to the select code of each such data message to pass data messages associated with the select code of the said selection means; cyclic data storage means for storing data messages; write means for storing data messages passed by said selection means at a first rate; write counter means connected to said write means for counting the number of data messages stored in said storage means; read-out means connected to said storage means for extracting data messages from said storage means at a second rate independent of said first rate; read counter means connected to said read-out means for counting the number of data messages extracted from said storage means; and inhibit means responsive to the counts in said write and read counter means for inhibiting operation of said write means when the counts of said write and read counter means indicate that said storage means contains data messages in all regions of said storage means which have not been extracted by said read-out means.
Claim 8
Dependent Claim
31 words
Apparatus according to claim 5 further including means responsive to said inhibit means for transmitting a message to said central computer indicative of a fully loaded condition in said storage means.
Claim 9
Dependent Claim
53 words
Apparatus according to claim 6 wherein said storage means has n regions addressed sequentially and cyclically, each of said first and second counters cyclically counting to n, said gate means being operable to provide said inhibit signal when the count in said first counter means equals the count in said second counter means.
Claim 10
Dependent Claim
53 words
Apparatus according to claim 5 wherein said storage means has n regions addressed sequentially and cyclically, each of said first and second counters cyclically counting to n, said gate means being operable to provide said inhibit signal when the count in said first counter means equals the count in said second counter means.
References Cited (Backward Citations)
US3579203A
Cited
US3656122A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-23 | 1977-01-22 | 1977-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-23 | 1981-01-22 | 1981-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-23 | 1985-01-22 | 1985-07-24 | $7700.00 | Window Closed / Lapsed |