US3579203A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Recirculating buffer memory
Assignee: Unisys Corp
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Filing: 1968-12-12
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Granted: 1971-05-18
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Expires: 1988-12-12
Abstract
Abstract The disclosure embodies a dynamic, first-in-first-out buffer memory and includes means for selectively and sequentially recirculating and advancing the relative positions of the binary encoded data therein.
Inventors
- 👤 Michael M Malmer Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:40
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/08; G06F5/085; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/188
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
253 words
A dynamic buffer memory comprising: delay means for storing data, said delay means being disposed between an input terminal and an output terminal and being divided into a plurality of character storage sections with each said character storage section being denominated in an ordered numbering system from a first input stage to a last output stage, recirculation means having one or more logical gating elements for selectively coupling said output terminal to said input terminal with no effective time delay, input means having one or more logical gating elements for selectively coupling a source of encoded data to said input terminal, output means having one or more logical gating elements for selectively coupling the output terminal of said delay means to an output of the buffer memory, monitor means selectively coupled to said delay means for continuously determining the data content of each of said character storage sections without removing said data from said character storage sections, transfer means coupled between said output terminal and said input terminal of said delay means and including a temporary storage for storing one bit of encoded data read from said output terminal of said delay means, said transfer means being operable to shift data stored in a lower order character storage section of said delay means to a higher order character storage section when said monitor means detects no data stored in such higher order character storage section, and control means for synchronizing the operations of and selectively enabling said data input, recirculation and transfer means.
Claim 2
Dependent Claim
253 words
A dynamic buffer memory comprising: delay means for storing data, said delay means being disposed between an input terminal and an output terminal and being divided into a plurality of character storage sections with each said character storage section being denominated in an ordered numbering system from a first input stage to a last output stage, recirculation means having one or more logical gating elements for selectively coupling said output terminal to said input terminal with no effective time delay, input means having one or more logical gating elements for selectively coupling a source of encoded data to said input terminal, output means having one or more logical gating elements for selectively coupling the output terminal of said delay means to an output of the buffer memory, monitor means selectively coupled to said delay means for continuously determining the data content of each of said character storage sections without removing said data from said character storage sections, transfer means coupled between said output terminal and said input terminal of said delay means and including a temporary storage for storing one bit of encoded data read from said output terminal of said delay means, said transfer means being operable to shift data stored in a lower order character storage section of said delay means to a higher order character storage section when said monitor means detects no data stored in such higher order character storage section, and control means for synchronizing the operations of and selectively enabling said data input, recirculation and transfer means.
Claim 3
Dependent Claim
40 words
A dynamic buffer memory as defined by claim 1 wherein said control means has timing means including an oscillator, the output of which is logically gated to define subdivisions of said delay means into count, character and word times respectively.
Claim 4
Dependent Claim
45 words
A dynamic buffer memory as defined by claim 2 wherein said temporary storage comprises a bistable flip-flop selectively coupled between the input and output terminals of said delay means by separate logic gates for setting a binary ''''one'''' and a binary ''''two'''' into said flip-flop.
Claim 5
Dependent Claim
31 words
A dynamic buffer memory as defined by claim 3 wherein said monitor means comprises a multistaged binary counter, said counter being selectively coupled between said timing means and said transfer means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |