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US3740646A
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Testing of non-linear circuits by accumulated result comparison
Assignee: International Business Machines Corp
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Filing: 1971-08-02
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Granted: 1973-06-19
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Expires: 1991-08-02
Abstract
Abstract A method and apparatus for testing complex, nonlinear, binary circuits by applying a bilevel input electrical signal pattern, made up of a plurality of pattern increments, in sequence, each comprising a plurality of parallel bilevel signals to a plurality of corresponding input points in a circuit reference. A resulting output signal pattern is sensed at a plurality of output points in the circuit reference. The output signal pattern is made up of a plurality of pattern increments, in sequence, each respectively resulting from one of the input pattern increments. The output patten increments are added in parallel to provide a reference total. The procedure is then repeated using the identical input electrical signal pattern, except that the actual circuit to be tested is used in place of the circuit reference. The signal pattern is applied to a plurality of input points in the circuit being tested corresponding to the input points in the circuit reference, and the resulting output is sensed at a plurality of output points in said circuit corresponding to the output points in the reference. The resulting output patter increments are then added together in the same manner to provide a total for the tested circuit. This should be equal to the reference total; otherwise, the tested circuit is defective.
Inventors
- 👤 Mahon M Mc
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:29
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318385; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
244 words
A method for testing non-linear circuits having n level logic comprising: applying to a plurality of input points in a circuit reference corresponding to the circuit being tested, an n level input electrical signal pattern made up of a plurality of pattern increments, in sequence, each comprising a plurality of parallel n level signals, each signal being respectively applied to one of said plurality of input points; sensing at a plurality of output points in said circuit reference, a resulting n level output signal pattern made up of a plurality of pattern increments, in sequence, respectively resulting from the input pattern increments; adding together the n level values of said plurality of output pattern increments to provide a reference total; applying an identical n level input electrical signal pattern to a plurality of input points in the circuit being tested corresponding to the plurality of input points in said circuit reference; sensing at a plurality of output points in the circuit being tested corresponding to the plurality of output points in said circuit reference, the resulting n level output signal pattern made up of a plurality of pattern increments, in sequence, resulting from the input pattern increments to the circuit being tested; adding together the n level values of said plurality of output pattern increments from the circuit being tested to provide a tested circuit total; and comparing the reference total with the tested circuit total to determine whether the tested circuit is defective.
Claim 2
Independent Claim
244 words
A method for testing non-linear circuits having n level logic comprising: applying to a plurality of input points in a circuit reference corresponding to the circuit being tested, an n level input electrical signal pattern made up of a plurality of pattern increments, in sequence, each comprising a plurality of parallel n level signals, each signal being respectively applied to one of said plurality of input points; sensing at a plurality of output points in said circuit reference, a resulting n level output signal pattern made up of a plurality of pattern increments, in sequence, respectively resulting from the input pattern increments; adding together the n level values of said plurality of output pattern increments to provide a reference total; applying an identical n level input electrical signal pattern to a plurality of input points in the circuit being tested corresponding to the plurality of input points in said circuit reference; sensing at a plurality of output points in the circuit being tested corresponding to the plurality of output points in said circuit reference, the resulting n level output signal pattern made up of a plurality of pattern increments, in sequence, resulting from the input pattern increments to the circuit being tested; adding together the n level values of said plurality of output pattern increments from the circuit being tested to provide a tested circuit total; and comparing the reference total with the tested circuit total to determine whether the tested circuit is defective.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein the circuits being tested have bilevel logic and the signals in said pattern are bilevel signals.
Claim 4
Dependent Claim
19 words
The method of claim 1 wherein said circuit reference is a simulated circuit corresponding to the circuit being tested.
Claim 5
Dependent Claim
12 words
The method of claim 3 wherein said simulated circuit is computer simultated.
Claim 6
Dependent Claim
15 words
The method of claim 1 wherein said circuit being tested is an integrated semiconductor circuit.
Claim 7
Dependent Claim
14 words
The method of claim 1 wherein said circuit being tested is a combinational circuit.
Claim 8
Independent Claim
387 words
A method for testing non-linear sequential circuits having n level logic comprising: detecting whether an n level electrical input signal pattern made up of a plurality of changing pattern increments, in sequence, each comprising a plurality of n level signals to be respectively applied to one of a plurality of input points in the circuit to be tested, produces critical race conditions in the sequential circuit to be tested, which race conditions result in an indeterminate signal level at at least one of a plurality of output points in the circuit to be tested during the application of one or more of said pattern increments to the circuit to be tested; storing the locations of the output points having indeterminate levels resulting from the application of each pattern increment; applying to a plurality of input points in a circuit reference corresponding to said plurality of input points in the circuit to be tested, said n level electrical signal pattern; sensing at a plurality of output points in said circuit reference corresponding to said plurality of output points in the circuit to be tested, a resulting n level output signal pattern mAde up of a plurality of pattern increments, in sequence, respectively resulting from the input pattern increments; adding together the n level values of all of said plurality of output pattern increments, except the output signals in each output pattern increment which are at output points previously detected to be at indeterminate signal levels, based upon said stored locations, to thereby provide a reference total; applying said identical n level input signal pattern to said plurality of input points in the circuit being tested; sensing at said plurality of output points in the circuit being tested, the resulting n level output signal pattern made up of a plurality of pattern increments, in sequence, respectively resulting from the input pattern increments to the circuit being tested; adding together the n level values of all of said plurality of output pattern increments from the circuit being tested, except the output signals in each output pattern increment which are at output points previously detected to be at indeterminate signal levels, based upon said stored locations, to thereby provide a tested circuit total; and, comparing the reference total with the tested circuit total to determine whether the tested circuit is defective.
Claim 9
Independent Claim
387 words
A method for testing non-linear sequential circuits having n level logic comprising: detecting whether an n level electrical input signal pattern made up of a plurality of changing pattern increments, in sequence, each comprising a plurality of n level signals to be respectively applied to one of a plurality of input points in the circuit to be tested, produces critical race conditions in the sequential circuit to be tested, which race conditions result in an indeterminate signal level at at least one of a plurality of output points in the circuit to be tested during the application of one or more of said pattern increments to the circuit to be tested; storing the locations of the output points having indeterminate levels resulting from the application of each pattern increment; applying to a plurality of input points in a circuit reference corresponding to said plurality of input points in the circuit to be tested, said n level electrical signal pattern; sensing at a plurality of output points in said circuit reference corresponding to said plurality of output points in the circuit to be tested, a resulting n level output signal pattern mAde up of a plurality of pattern increments, in sequence, respectively resulting from the input pattern increments; adding together the n level values of all of said plurality of output pattern increments, except the output signals in each output pattern increment which are at output points previously detected to be at indeterminate signal levels, based upon said stored locations, to thereby provide a reference total; applying said identical n level input signal pattern to said plurality of input points in the circuit being tested; sensing at said plurality of output points in the circuit being tested, the resulting n level output signal pattern made up of a plurality of pattern increments, in sequence, respectively resulting from the input pattern increments to the circuit being tested; adding together the n level values of all of said plurality of output pattern increments from the circuit being tested, except the output signals in each output pattern increment which are at output points previously detected to be at indeterminate signal levels, based upon said stored locations, to thereby provide a tested circuit total; and, comparing the reference total with the tested circuit total to determine whether the tested circuit is defective.
Claim 10
Dependent Claim
37 words
The method of claim 7 wherein the output signals in each of the output points detected to be at the indeterminate signal level are excepted from being added by inhibiting the sensed signals at said output points.
Claim 11
Dependent Claim
22 words
The method of claim 7 wherein the circuits being tested have bilevel logic and the signals in said pattern are bilevel signals.
Claim 12
Dependent Claim
19 words
The method of claim 7 wherein said circuit reference is a simulated circuit corresponding to the circuit being tested.
Claim 13
Dependent Claim
12 words
The method of claim 10 wherein said simulated circuit is computer simulated.
Claim 14
Dependent Claim
15 words
The method of claim 7 wherein the circuit being tested is an integrated semiconductor circuit.
Claim 15
Dependent Claim
155 words
The method of claim 7 wherein detecting whether said indeterminate signal levels exist is carried out by converting the n level signal pattern to an (n+1) level signal pattern in which the n levels represent the n levels in the circuit logic and said 1 level represents an indeterminate level in said circuit logic; applying said (n+1) signal pattern to a reference simulation of the circuit to be tested adapted to receive said (n+1) level signal pattern at a plurality of input points corresponding to the input points in the circuit being tested and to provide a resulting (n+1) signal level output at a plurality of output points corresponding to the output points in the circuit to be tested; and, detecting whether said indeterminate logic level exists at one or more of said output points in said simulation as a result of the application of a pattern increment to the input points in said simulation.
Claim 16
Dependent Claim
24 words
The method of claim 13 wherein said original signal pattern is a bilevel pattern and said converted signal pattern is a three-level signal pattern.
Claim 17
Dependent Claim
119 words
Apparatus for testing non-linear circuits having n level logic comprising: means for generating an n level electrical signal test pattern made up of a plurality of pattern increments, in sequence, each comprising a plurality of parallel n level signals; means for applying said test pattern to a plurality of input points in the circuit being tested; means for sensing at a plurality of output points in the circuit being tested, a resulting n level output signal pattern made up of a plurality of pattern increments, in sequence, respectively resulting from the applied test pattern increments; and means for adding together the n level values of said sensed plurality of output pattern increments to provide a total n level value.
Claim 18
Dependent Claim
119 words
Apparatus for testing non-linear circuits having n level logic comprising: means for generating an n level electrical signal test pattern made up of a plurality of pattern increments, in sequence, each comprising a plurality of parallel n level signals; means for applying said test pattern to a plurality of input points in the circuit being tested; means for sensing at a plurality of output points in the circuit being tested, a resulting n level output signal pattern made up of a plurality of pattern increments, in sequence, respectively resulting from the applied test pattern increments; and means for adding together the n level values of said sensed plurality of output pattern increments to provide a total n level value.
Claim 19
Dependent Claim
25 words
The apparatus of claim 15 wherein the circuit being tested has bilevel logic and the signals in said test and output patterns are bilevel signals.
Claim 20
Dependent Claim
14 words
The apparAtus of claim 15 wherein the circuit being tested is a simulated circuit.
Claim 21
Dependent Claim
12 words
The apparatus of claim 17 wherein said simulated circuit is computer simulated.
Claim 22
Dependent Claim
36 words
The apparatus of claim 15 wherein said means for adding is a parallel adder having a plurality of parallel bit positions corresponding to and connected to said plurality of output points in said circuit being tested.
Claim 23
Dependent Claim
58 words
The apparatus of claim 19 wherein said parallel adder has one bit position for each of said plurality of output points in the circuit being tested plus x bit positions for carries where the number of carries x is determined by the formula 2x m, with m being the number of sequential increments in the applied test pattern.
Claim 24
Dependent Claim
152 words
Apparatus for testing non-linear circuits having bilevel logic comprising: means for generating a bilevel electrical signal test pattern made up of a plurality of pattern increments, in sequence, each comprising a plurality of parallel bilevel signals; means for applying said test pattern to a plurality of input points in the circuit being tested; at least on shift register having a plurality of bit positions; means for receiving, at at least one output point in the circuit being tested, a resulting bilevel output signal pattern made up of a plurality of pattern increments, in sequence, respectively resulting from the input pattern increments, and for applying the signal pattern received from one of said output points to one of said shift registers; and, adding means for adding together in parallel the bilevel values in the bit positions in said shift register resulting from the application of the output pattern increments to said shift register.
Claim 25
Dependent Claim
152 words
Apparatus for testing non-linear circuits having bilevel logic comprising: means for generating a bilevel electrical signal test pattern made up of a plurality of pattern increments, in sequence, each comprising a plurality of parallel bilevel signals; means for applying said test pattern to a plurality of input points in the circuit being tested; at least on shift register having a plurality of bit positions; means for receiving, at at least one output point in the circuit being tested, a resulting bilevel output signal pattern made up of a plurality of pattern increments, in sequence, respectively resulting from the input pattern increments, and for applying the signal pattern received from one of said output points to one of said shift registers; and, adding means for adding together in parallel the bilevel values in the bit positions in said shift register resulting from the application of the output pattern increments to said shift register.
Claim 26
Dependent Claim
14 words
The apparatus of claim 21 wherein the circuit being tested is a simulated circuit.
Claim 27
Dependent Claim
30 words
The apparatus of claim 21 having a plurality of output points and a plurality of corresponding shift registers, each of which is respectively associated with one of said output points.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-18 | 1976-12-18 | 1977-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-18 | 1980-12-18 | 1981-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-18 | 1984-12-18 | 1985-06-19 | $7700.00 | Window Closed / Lapsed |