Triggered flip-flop

Claim 2

A multivibrator circuit including a flip-flop circuit, input means for receiving a trigger signal, control means connected to said flip-flop circuit and to said input means, said control means including at least one pair of complementary conductivity type semiconductor devices, said control means adapted to assume different operating conditions in accordance with the status of said flip-flop circuit, and said control means adapted to supply a signal to said flip-flop circuit in response to the application of a trigger signal to said input means such that the status of said flip-flop circuit changes.

Claim 3

The multivibrator circuit recited in claim 1 wherein said flip-flop circuit includes a pair of semicon-ductor devices which are cross-coupled by nonreactive means.

Claim 4

The multivibrator circuit recited in claim 1 wherein said control means includes coupling means connected between said pair of complementary conductivity type semiconductor devices and said flip-flop circuit.

Claim 5

The multivibrator circuit recited in claim 1 wherein said control means includes two pairs of complementary conductivity semiconductor devices, each of said pairs of semiconductor devices being in a different operating state in accordance with the status of said flip-flop circuit.

Claim 6

In combination, first and second transistors cross-coupled to provide a flip-flop circuit, trigger signal supplying means, first and second control circuit means, each including a pair of complementary conductivity type semiconductor devices connected in a trigger circuit configuration, said first and second control circuit means connected to receive a signal from said first and second transistors, respectively, such that one of said first and second control circuit means is enabled as a function of the operating states of said first and second transistors of said flip-flop circuit, first clamping means connected between said first control circuit means and said first transistor, second clamping means connected between said second control circuit means and said second transistor, said trigger signal supplying means connected to said first and second clamping means and to said first and second control circuit means in order to supply trigger signals thereto such that said one of said first and second control circuit means which was previously enabled is rendered operative and the associated clamping is rendered inoperative while the other of said first and second control circuit means remains inoperative and the associated clamping means is rendered operative and thereby to supply a signal to said flip-flop circuit to change the states of said first and second transistors.

Claim 7

In combination, first and second transistors cross-coupled to provide a flip-flop circuit, trigger signal supplying means, first and second control circuit means, each including a pair of complementary conductivity type semiconductor devices connected in a trigger circuit configuration, said first and second control circuit means connected to receive a signal from said first and second transistors, respectively, such that one of said first and second control circuit means is enabled as a function of the operating states of said first and second transistors of said flip-flop circuit, first clamping means connected between said first control circuit means and said first transistor, second clamping means connected between said second control circuit means and said second transistor, said trigger signal supplying means connected to said first and second clamping means and to said first and second control circuit means in order to supply trigger signals thereto such that said one of said first and second control circuit means which was previously enabled is rendered operative and the associated clamping is rendered inoperative while the other of said first and second control circuit means remains inoperative and the associated clamping means is rendered operative and thereby to supply a signal to said flip-flop circuit to change the states of said first and second transistors.

Claim 8

The combination recited in claim 5 wherein each of said first and second clamping means includes transistor means.

Claim 9

The combination recited in claim 5 wherein said first and second transistors are cross-coupled by nonreactive impedance means.

Claim 10

The combination recited in claim 5 wherein said first and second transistors each have base, emitter and collector electrodes, said first clamping means includes a third transistor having base, emitter and collector electrodes, said second clamping means includes a fourth transistor having base, emitter and collector electrodes, the emitter electrodes of said third and fourth transistors, being connected to a reference potential source, the collector electrodes of said third and fourth transistors being connected to base electrodes of said first and second transistors respectively, the base electrodes of said third and fourth transistors being connected to said trigger signal supplying means, each said pair of complementary conductivity type semiconductor devices of said first and second control circuit means comprising a pair of transistors having base, emitter and collector electrodes, the emitter electrode of one of the transistors in each pair of transistors being connected to said reference potential source, the emitter electrode of the other of the transistors in each pair of transistors being connected to the base electrode of said third and fourth transistors respectively, the base electrode of said one transistor being connected to the collector electrode of said other transistor and to the collector electrode of the associated one of said first and second transistors respectively, and the base electrode of said other transistor being connected to the collector electrode of said one transistor.

Claim 11

In combination: a flip-flop which includes two transistors, each having an input, output and control electrode, the control electrode of each transistor connected to the output electrode of the other transistor; two switch means, one connected between one electrode of one transistor and a point of reference potential and the other connected between the corresponding electrode of the other transistor and said point of reference potential; and means for alternately momentarily closing said switch means one at a time, comprising a first pair of transistors of complementary conductivity types coupled between one transistor of said flip-flop and one of the switch means for controlling said one switch means and a secoNd pair of transistors of complementary conductivity types coupled between the other transistor of said flip-flop and the other of said switch means for controlling the other of said switch means, and means for concurrently applying trigger signals to said two switch means and to the first and second pairs of transistors of complementary conductivity types.

Claim 12

In combination: a flip-flop which includes two transistors, each having an input, output and control electrode, the control electrode of each transistor connected to the output electrode of the other transistor; two switch means, one connected between one electrode of one transistor and a point of reference potential and the other connected between the corresponding electrode of the other transistor and said point of reference potential; and means for alternately momentarily closing said switch means one at a time, comprising a first pair of transistors of complementary conductivity types coupled between one transistor of said flip-flop and one of the switch means for controlling said one switch means and a secoNd pair of transistors of complementary conductivity types coupled between the other transistor of said flip-flop and the other of said switch means for controlling the other of said switch means, and means for concurrently applying trigger signals to said two switch means and to the first and second pairs of transistors of complementary conductivity types.

Claim 13

The combination recited in claim 9 where each said pair of transistors of complementary conductivity type comprises transistors having base, emitter and collector electrodes with the base electrode of each transistor connected to the collector electrode of the other transistor.

Claim 14

In a circuit as set forth in claim 10, one transistor of said flip-flop supplying a signal of one sense to one base-collector connection of one pair of said complementary transistors for causing base-emitter current to flow through one transistor of said pair whereby the base of the other transistor of said pair is placed at a level to prime said other transistor, and the other transistor of said flip-flop supplying a signal of opposite sense to the corresponding base-collector connection of the other pair for disabling both transistors of said other pair.

Claim 15

The combination recited in claim 9 wherein said first pair of transistors of complementary symmetry type is coupled between the output electrode of one of said flip-flop transistors and the switch means which is coupled to the same transistor, and said second pair of transistors of complementary symmetry type is coupled between the output electrode of the other transistor of said flip-flop and the switch means which is coupled to said other transistor of said flip-flop.

Claim 16

The combination recited in claim 9 wherein each said switch means comprises a transistor having a control electrode adapted to receive a trigger signal and having a conduction path connected between the control electrode of a separate one of the flip-flop transistors and said point of reference potential.

Claim 17

The combination recited in claim 13 wherein said means for concurrently applying trigger signals comprises a trigger input terminal coupled to the control electrodes of the transistors comprising said two switch means and to one transistor of each of said pair of transistors of complementary conductivity types.